Alliance Semiconductor Corporation

Eric Voelkel

Ajit K Medhekar

An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage. When the output signal is a logic 0, the feedback circuit turns the pull-up and pull-down transistors on and off, respectively, and when the output signal is a logic 1, the feedback circuit turns the pull-up and pull-down transistors off and on, respectively. Once the output signal has reached the desired pre-output signal level intermediate to the normal logic 0 and logic 1 levels, the feedback circuit rams off both the pull-up and pull-down transistors. Accordingly, an output signal at the desired pre-output signal level is provided with no DC power consumption by the output stage.

Output buffer circuit with low power pre-output drive

A design approach for a tree structure multiplexer produces a compact circuit layout by reducing the required number of transistors. The multiplexer is used to perform a binary decode of the input signals to generate a single selection of one of a number of potential outputs. since the inputs undergo a binary decode, the number of outputs is equal to 2.sup.x, where x is the number of inputs.

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Eric Voelkel