Semtech Corporation

Semtech Neuchatel Sa

Eric Vandel

Chaouki Rouaissia

Krishna Shivaram

Aravind Heragu

A FIR filter (), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device () configured to generate a first current signal (i) proportional to the input signal; a first analog switch () commuted in n by a first digital gate signal (ϕ) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor () when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

Analog FIR filter

A proximity sensor has a sensing node. A radio frequency signal is received at the sensing node. The radio frequency signal is coupled to an intermediate node through a first capacitor. The radio frequency signal is coupled from the intermediate node to a ground node through a second capacitor. An RF amplifier is coupled to the sensing node. The radio frequency signal is generated using the RF amplifier. A third capacitor is coupled between the RF amplifier and the sensing node. An antenna is coupled to the sensing node. The radio frequency signal is transmitted using the antenna. A capacitance of the antenna is measured using the proximity sensor. The capacitance of the antenna is compared to a threshold to determine proximity of a conductive object. An inductor is coupled between the sensing node and the antenna. A shielding area is coupled to the intermediate node.

Method and device for reducing radio frequency interference of proximity and touch detection in mobile devices

A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector.

Semiconductor device and method for accurate clock domain synchronization over a wide frequency range

Described herein is a distributed analog loop filter that can be employed in a phase locked loop or a delay locked loop. A circuit block of the distributed analog loop filter includes at least two parallel equivalent circuit elements. The parallel equivalent circuit elements each have an input line. The input lines for each of the parallel equivalent circuit elements are activated sequentially, one after the other. The parallel equivalent circuit elements have sequentially produced outputs that are also activated sequentially, one after another. The parallel equivalent circuit elements extend the tuning range of distributed analog filter while reducing noise associated with the distributed analog filter.

Analog loop filter systems, apparatus, and methods

Described herein is a low-voltage multi-stage interleaver. The interleaver includes at least a first interleaver stage and a second interleaver stage. The first interleaver stage is either blocked or operating in a saturation region. The first interleaver stage facilitates cancellation of DC current, including a biasing current, so that the second interleaver stage receives no DC current input. The second interleaver stage is either blocked or operating in a linear region to allow the second interleaver stage to act as a passive current switch.

Low voltage multi-stage interleaver systems, apparatus and methods

Phase locked loop circuit () having a double entry VCO () and two independent charge pumps (), each connected with one of the entries of the VCO. Each of the VCO entries has a different gain coefficient, thereby allowing a better optimisation and control of the device bandwidth and a reduced phase noise. Can be employed in radio transmitters and/or receivers and allows simultaneous and precise FM modulation both inside and outside the PLL bandwidth.

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Concise, Switzerland

Eric Vandel