Advanced Micro Devices Corporation

Eric Tsin-Ho Leung

Bahadir Erimli

Ching Yu

Ian Lam

Shashank C Merchant

Robert Alan Williams

John Mingyung Chiang

Chandan Egbert

Xiaohua Zhuang

Edward Yang

Vallath Nandakumar

Ian S Crayford

Thomas J Runaldue

Denise Kerstein

Jayant Kadambi

Philip Simmons

Jinqlih Sang

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Apparatus and method for programmable memory access slot assignment

A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.

Two-part memory address generator

A network switch arrangement and method for providing a common architecture for queuing and dequeuing of data frames as they are transferred from a switch port to an external memory and similarly retrieved from the external memory to the switch port, irrespective of the particular data rate of the port. Logic controlling the actual data path is partitioned from logic responding to port data rate information by providing a &ldquo;handshaking&rdquo; communication arrangement between the two logics independent of the data rate. Hence, scalability of the data path over a wide range of data rates may be achieved while maintaining a single, common logic architecture.

Common scalable queuing and dequeuing architecture and method relative to network switch data rate

A method and apparatus in a network switch port for providing queuing of data frames as they are transferred from a switch port to an external memory. Multiple buffers within the external memory used to store a single data frame are linked together by writing a next buffer location in each buffer header. Storing linking information within each buffer eliminates the need for a separate memory for storing all the buffer locations used to store a data frame, thereby reducing the complexity and cost of the network switch port.

Method and apparatus for queuing data frames in a network switch port

An arrangement and method of operating a network switch arrangement in a packet switched network connects a plurality of multiport network switches which is in a circular, serial manner so that data is transferable between the network switches only unidirectionally. When it is determined that data is to be transmitted from a first network switch to a port in a second network switch, the data is transmitted over an expansion bus from the first network switch to the second network switch in a continuous stream of data bursts. This extremely fast transmission between the networks switches allows multiple multiport network switches to be cascaded together to effectively form a single network switch with at least twice as many ports.

Apparatus and method for cascading multiple network switch devices

A multiport data communication system for switching data packets between ports having a memory storing received data packets and a plurality of ports for transmitting and receiving data packets. Each transmit port has a transmit queue storing data packets to be transmitted from the respective port. The system includes a plurality of output queues, each corresponding to a respective port and storing frame pointers that point to where the data packets are stored in the memory. A plurality of dequeuing logic circuitry is provided corresponding to the plurality of ports. Each dequeuing logic circuitry reads respective frame pointers from the plurality of queues, reads the respective data packets corresponding to the respective frame pointers from the memory, and writes each read data packet to the corresponding transmit queue. The operations of each dequeuing logic circuitry are carried out in a pipelined manner in order to fully utilize the bandwidth of the external memory and speed up the dequeuing process. Consequently, there is no idle time between completing of reading of one data packet from the memory and beginning of reading of a subsequent data packet from the memory or between completing writing of one data packet to the corresponding transmit queue and 4.

Dequeuing logic architecture and operation in a multiport communication switch

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.

Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port

A multiport data communication system for switching data packets between ports comprising a plurality of receive ports for receiving data packets, a memory storing the received data packets, and a plurality of transmit ports each having a transmit queue. Logic circuitry for each transmit port controls reading from memory data corresponding to each data packet to be transmitted from the respective transmit port, reassembling the data read from the memory, and writing the reassembled data to the corresponding transmit queue. A monitoring circuit monitors the received data packets prior to storing them in the memory and determines whether a respective data packet should have the VLAN tag inserted/stripped/modified and/or the Device ID inserted/stripped. Reassembling the data includes inserting/stripping/modifying a VLAN tag and/or inserting/stripping a Device ID into the data read from the memory in accordance with a result of the determination of the monitoring circuit prior to writing the reassembled data into the corresponding transmit queue.

Frame assembly in dequeuing block

A multiport data communication system for switching data packets between ports includes a plurality of receive ports for receiving data packets, a plurality of transmit ports for transmitting data packets, circuitry deciding whether each received data packet is one of high priority and low priority, and a memory for storing each received data packet. A memory location designator is provided for each data packet indicating where the corresponding data packet is stored in the memory and a plurality of queuing devices corresponding to the plurality of transmit ports queue the memory location designators. Each queuing device has a high priority queue queuing memory location designators corresponding to data packets of high priority to be retrieved from the memory an transmitted by the respective transmit port and a low priority queue queuing memory location designators corresponding to data packets of low priority to be retrieved from the memory and transmitted by the respective transmit port. Transferring circuitry transfers the data packets from the memory to a transmit queue corresponding to each respective transmit port and includes logic circuitry corresponding to each transmit queue. The logic circuitry determines whether the low priority queue of a respective queuing device has a memory location designator for a data packet to be retrieved from the memory and sent to the corresponding transmit queue only when the high priority queue of the respective queuing device is empty of memory location designators.

Method and apparatus for processing high and low priority frame data transmitted in a data communication system

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.

Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port

A multiport data communication system for switching data packets between ports comprising a plurality of receive ports for receiving data packets, a memory storing the received data packets, and a plurality of transmit ports each having a transmit queue. Logic circuitry for each transmit port controls reading of a data packet from memory, provides a control signal indicating an end of reading the data packet from the memory, decides whether a length of the read data packet is to increase, decrease, or remain the same, controls writing the read data packet to a corresponding transmit queue in accordance with the decision, and provides a signal indicating an end of writing the data packet to the transmit queue. To generate the end of reading of the data packet from memory, the logic circuitry determines a number of read operations necessary to read the data packet, corresponding to read address data from the memory, counts each read operation, and provides the signal indicating an end of reading the data packet from the memory when the counted read operations are equal to the number of determined read operations. To generate the end of writing the data packet to the transmit queue, the logic circuitry determines a number of write operations necessary to write the data packet which is modified/unmodified in accordance with decision as to whether a length of the read data packet is to increase, decrease, or remain the same, counts each write operation, and provides the signal indicating an end of writing the data packet to the transmit queue when the counted write operations are equal to the number of determined write operations.

Method and apparatus for providing EOF for frame modification

A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated on a half-duplex network port by transmitting a phantom packet to a transmitting network station if the output buffer of a destination port exceeds a programmed high threshold, or if the output buffer of the destination port exceeds a low programmed threshold and the queue of free frame pointers falls below a low programmable threshold. The switch thus provides flexibility in providing selective collisions with transmitting stations to minimize the possibility of network congestion without wasting network bandwidth with unnecessary collisions.

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San Jose, CA, United States of America

Eric Tsin-Ho Leung