Cisco Technology, Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Eric Trehus

Kuan-Yuh Ko

John Gregory Favor

Stephan G Meier

Robert G Hathaway

Nicholas Leavy

Evan Gewirtz

James Forman

Karthik M Sadhasivam

Venkataraman Sukavanam

Anders K Fung

Bin Liang

A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Digital processor for processing long and short pointers and converting each between a common format

In one embodiment, when conditions are observed a wireless device keeps its radio circuitry powered down during a designated transmission window orchestrated by an associated Access Point (AP) for forwarding buffered broadcast and multicast data to reduce power consumption by the wireless device. The wireless device then temporarily powers up its radio circuitry to receive a beacon outside the designated transmission window. When the received beacon indicates buffered data, the wireless device transmits a request for a unicast transmission of the buffered data from the AP.

Saving power in a wireless network in the presence of multicast or broadcast data

A method and apparatus for virtual application of features to electronic messages is disclosed. When a device applies a set of features to an electronic message, one or more of the features may be virtually applied instead of actually applied. For example, instead of encrypting a payload portion of a packet and adding an encryption header, the packet may not be encrypted. However, an appropriate encryption header may still be included in the packet such that the packet appears to have been encrypted when other features are applied. Prior to sending the packet, the payload portion is actually encrypted, such as by using a hardware accelerator. Some implementations may use a dual processor router, in which the input/output processor controls the hardware accelerator, the routing processor performs the virtual application of a feature, and prior to sending the packet the input/output processor actually applies the virtually applied feature.

Virtual application of features to electronic messages

A transfer type selector selects a transfer type used for maintaining cache coherency according to address values used for accessing memory and is programmable so that different transfer types can be selected for different applications. In one embodiment, a table has different address ranges each having associated transfer types. Transfer type selection logic selects one of the transfer types associated with the address range containing the address in a memory transaction request.

Method and apparatus for selecting transfer types

Address based prefetch logic varies prefetching according to address values in read requests. The address based prefetch logic can vary how much data is initially read into a prefetch buffer or when a prefetch buffer is refilled to an initial prefetch amount. One advantage of the address based prefetch logic is that prefetching and prefetch buffer refill rates are tuned for particular application. This is important since the system controller ordinarily does not know how much data the master is requesting beyond the first data phase. The requested read address is used as a hint to determine how much prefetching needs to occur. Over prefetching wastes memory bandwidth, and potentially adds latency to other masters sharing common busses. Under prefetching may cause the system controller that is acting as a PCI target to terminate the master's read request, thus wasting PCI bandwidth, adding latency.

Method and apparatus for optimizing prefetching based on memory addresses

A computing device having multiple masters. The device includes a set of masters and at least one target with at least one bus that provides connecting between the masters and the target. A system controller operates to quiesce masters selected from the set of masters in response to an error message. A system error processor handles the error condition after the selected masters have been quiesced.

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San Jose, CA, United States of America

Eric Trehus