International Business Machines Corporation

Eric Todd Hennenhoefer

Jonathan Henry Raymond

Apparatus and method for emulating a circuit having at least one multiport RAM that requires at least two programmable device to be emulated. The multiport RAM has an array of storage elements, a read multiplexer, and a write multiplexer and is partitioned into a number of slices, each of which is capable of being programmed into one of an array of programmable devices. In one embodiment, each slice is another multiport RAM having the same depth, number of read ports, and number of write ports as the multiport RAM being emulated, but having a narrower width than the multiport RAM being emulated. In another embodiment, the multiport RAM is partitioned into read slices and write slices, which will typically be of different widths. The read slices comprise the read multiplexers. The write slices comprise the array of storage elements and the write multiplexers.

Apparatus and method for partitioning multiport rams

An optimized multiplexer structure reduces the cost in emulation gates in an emulator test system. Extra encoding and decoding logic is added to form a selector with multiple separate subblocks so that the data flow subblock has a reduced input/output (I/O) control path. The circuit reduces the number of control bits from N bits to log.sub.2 N bits.

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Essex Jct., VT, United States of America

Eric Todd Hennenhoefer