Lattice Semiconductor Corporation

Eric Ting

Jun Zhao

Yanhua Yi

William A Oswald

Xiaotao Chen

Michael Lesile Roy

Wenyi Feng

Ruofan Xu

In one embodiment of the invention, a computer-implemented method of configuring a programmable logic device (PLD) includes placing logical functions within logical resources of the PLD to implement a desired netlist; swapping the logical function of at least one logical resource with the logical function of at least one other logical resource within the PLD; and evaluating whether to accept or reject the swap using a simulated annealing process that calculates at least three cost function values based upon routing priority groups, timing priority groups, and a timing critical group.

Multi-priority placement for configuring programmable logic devices

Systems and methods provide techniques to support design specific testing for programmable logic devices in accordance with one or more embodiments. For example in one embodiment, a method of generating configuration data for a programmable logic device includes mapping a design for the programmable logic device, wherein the mapped design incorporates scan test logic; placing and routing the mapped design; and generating configuration data based on the mapped design, wherein the incorporated scan test logic is disabled and not selectable within the programmable logic device configured with the configuration data. The method may further include generating a second configuration data based on the mapped design, wherein the incorporated scan test logic is enabled and selectable within the programmable logic device configured with the second configuration data.

Scan chain systems and methods for programmable logic devices

Techniques for synchronizing data signals and clock signals of a programmable logic device (PLD) are provided. In one example, a method includes preparing an initial configuration of the PLD identifying a plurality of data paths associated with the data signals and a plurality of clock paths associated with the clock signals. The method also includes identifying a hold time violation associated with at least one of the data paths, wherein at least one of the clock signals is used to synchronize the data path. The method further includes selectively adjusting a delay period of a delay element of at least one of the clock paths associated with the clock signal to attempt to correct the hold time violation without concurrently attempting to correct any setup time violation associated with the data path.

Synchronization of data signals and clock signals for programmable logic devices

A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of conventional placed-switch, switch-box, and pseudo-arc connections. A hidden-switch connection between two functional elements in the PLD is represented in graphical displays generated by the programming tool as a curve (e.g., a diagonal straight line) from a jumper wire on the first functional element to another jumper wire on the second functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to an pin of the corresponding functional element and unconnected at the other end. A programming tool that supports hidden-switch connections can be used to program FPGAs and other PLDs having architectures that were not previously supported by conventional programming tools that do not support hidden-switch connections.

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Macungie, PA, United States of America

Eric Ting