Xilinx, Inc.

Xilnix, Inc.

Nooma Bio, Inc.

Oxford Nanopore Technologies Limited

Eric Thorne

Nigel G Herron

Qingqi Wang

Robert W Wells

Robert D Patrie

Zhi-min Ling

Glenn O'Rourke

Yuezhen Fan

Stephen M Trimberger

Anthony Correale, Jr

Shahin Toutounchi

William Dunbar

Inderjit Singh

Raghunandan Chaware

Himanshu J Verma

Xiao-Yu Li

David Mark

Feng Wang

Ganesh Hariharan

Michael A Summers

Anthony P Calderone

Thomas Anderson Dick

Michael M Matera

Tarek Eldin

Reto Stamm

David E Schweigler

Michael Summers

Two-pore devices and method for sequencing are described. A two-pore device can include first chamber, a second chamber, and a third chamber, wherein the first chamber is in communication with the second chamber through a first nanopore, and wherein the second chamber is in communication with the third chamber through a second nanopore. The device can also include sensing circuitry for measuring electrical signals associated with a target at a nanopore, and control circuitry for controlling motion of the target at a nanopore. The device can include and/or switch between sensing and control modes for each of the first nanopore and the second nanopore. Sequencing methods can implement a two-pore device in relation to translocation of a target through one or more nanopores, switching between sensing and control modes as appropriate, and measuring aspects of the target using in sensing modes.

Dual pore&#x2014;control and sensor device

A method of enabling the use of a programmable device having impaired circuitry includes determining one or more locations of the impaired circuitry of the programmable device; generating a defect map for the programmable device based on the determined locations of the impaired circuitry; generating a plurality of configuration bitstreams to implement a circuit in the programmable device; selecting one of the plurality of configuration bitstreams that does not use the impaired circuitry indicated by the defect map; and programming the programmable device with the selected configuration bitstream.

Increased usable programmable device dice

A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Integrated circuit package testing

A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated circuit. The first path is coupled in a ring oscillator, and a first delay is determined. A second path is formed by coupling a second portion of the conductive lines together. The second portion is the first portion except for at least a first conductive line in the first portion of the conductive lines being swapped for a second conductive line. The second conductive line is associated with a second region of the integrated circuit. The second path is coupled in the ring oscillator circuit. A second delay is determined, and an incremental difference between the first delay and the second delay may be determined.

Method for determining interconnect line performance within an integrated circuit

The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.

Test circuit for and method of identifying a defect in an integrated circuit

A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Testing a programmable logic device with embedded fixed logic using a scan chain

Apparatus for testing an interconnecting logic fabric

A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.

Method and apparatus for testing circuitry embedded within a field programmable gate array

Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

Providing fault coverage of interconnect in an FPGA

A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Fault emulation testing of programmable logic devices

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Santa Cruz, CA, United States of America

Eric Thorne