Texas Instruments Corporation

Eric Thierry Peeters

Jin-Meng Ho

Per Torstein Roine

Erik Newton Shreve

John Anthony Rodriguez

Gregory Allen North

Prithvi Shankar Yeyyadi Anantha

Ruchi Shankar

Shobhit Singhal

Robin Osa Hoel

Aniruddha Periyapatna Nagendra

Prachi Mishra

William Francis Kraus

Manuel Gilberto Aguilar

Hamza Fraz

A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.

Resource access in a microcontroller

An electronic device, in disclosed embodiments, includes an antenna, transceiver circuitry coupled to the antenna, a memory configured to store a first operation key and instructions, and a processor coupled to the transceiver and to the memory. The processor is configured to execute the instructions stored in the memory to cause the electronic device to, in response to receiving a first transmission containing an encrypted version of a second operation key that is encrypted by the first operation key, decrypt the encrypted version of the second operation key using the first operation key to recover the second operation key, store the second operation key in the memory, transmitting, by a transmitter of the electronic device, a second transmission that contains the first operation key and a command.

Certificate-based pairing of key fob device and control unit

A method for pairing a key fob with a control unit is provided. The key fob executes an ID authenticated key agreement protocol with a pairing device based on a key fob identification to authenticate one another and to generate a first encryption key. The pairing device encrypts a control unit identification using the first encryption key. The key fob receives the encrypted control unit identification transmitted from the pairing device. The key fob then executes an ID authenticated key agreement protocol with the control unit based on the control unit identification to authenticate one another and to generate a second encryption key. The key fob then receives an operational key transmitted from the control unit that is encrypted with the second encryption key.

ID-based control unit-key fob pairing

A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

Processor with hardware supported memory buffer overflow detection

A method of performing finite field addition and doubling operations in an elliptic curve cryptography (ECC) authentication scheme as a countermeasure to side-channel attack. The addition and doubling operations are executed using atomic patterns that involve the same sequence and number of operation types, so that the noise consumption and electromagnetic emanation profile of circuitry performing the operations is identical regardless of operation. A subtraction operation using such an atomic pattern is also disclosed.

Homogenous atomic pattern for double, add, and subtract operations for digital authentication using elliptic curve cryptography

An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.

Thread ownership of keys for hardware-accelerated cryptography

A control unit, in a disclosed embodiment, includes a transceiver, memory, and a processor. The processor is coupled to the transceiver and memory and executes instructions from the memory to cause the control unit to receive a first transmission containing a certificate, verify the authenticity of the certificate, and, after verifying authenticity of the certificate, execute a public key agreement protocol to generate a first common secret encryption key, receive a second transmission containing an encrypted first public key that is encrypted by the first common secret encryption key, decrypt the encrypted first public key using the first common secret encryption key to determine the first public key, execute a public key agreement protocol to generate a second common secret encryption key, generate an operational key, encrypt the operational key using the second common secret encryption key, and transmit the encrypted operational key.

A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.

Random number generation with ferroelectric random access memory

A key fob device, in one embodiment, includes a transceiver that receives and sends signals, a memory that stores a public key and a certificate of authenticity associated with the key fob device, and a processor coupled to the transceiver and memory. The processor is configured to execute instructions causing the key fob device to transmit the public key and the certificate of authenticity, execute a public key agreement protocol to generate a common secret encryption key, and receive an operation key encrypted with the common secret encryption key.

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Frisco, TX, United States of America

Eric Thierry Peeters