Lightspeed Semiconductor Corporation

Lsi Logic Corporation

Seeq Technology, Incorporated

Otrsotech, Limited Liability Company

Lightspeed Logic, Inc.

Lsi Logic Cororation

Seeo Technology, Incorporated

Eric T West

Stephen F Dreyer

Robert X Jin

Shridhar K Mukund

Lyle Smith

Eric F Dellinger

Donald W Alderrou

Kathy L Peng

David Galbi

Robert Olah

Bingda Brandon Wang

Rabi Sengupta

Chit-Ah Mak

Pat Hom

Steven Eplett

An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Increased effective flip-flop density in a structured ASIC

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

Transparent test method and scan flip-flop

An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, each individual flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

ASIC routing architecture

A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.

Method and apparatus for built-in self-test of logic circuits with multiple clock domains

A method operates a media access control device. The method includes (a) detecting the assertion of a flow control condition, (b) generating a PAUSE frame in response to the detection of a flow control condition, the PAUSE frame directing a remote device to PAUSE for a first amount of time, (c) causing the media access device to wait for a second amount of time, the second amount of time being less than or equal to the first amount of time, and (d) generating, upon expiration of the second amount of time and the continued assertion of the flow control condition, an additional PAUSE frame directing a remote device to PAUSE for a first amount of time.

Automatic LAN flow control mechanisms

Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.

Function block architecture with variable drive strengths

A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

High speed differential receiver

In a 100BASE-T4 protocol network, the &ldquo;carrier_status&rdquo; signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Method and apparatus for using synthetic preamble signals to awaken repeater

An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Apparatus and method for providing multiple channel clock-data alignment

Pre-formatted MAC Control PAUSE frames are generated by a MAC device rather than by a switch. These may be automatically generated and transmitted upon the occurrence of a full or near full condition in the input buffer of the MAC device. The MAC device, upon receipt of a MAC Control PAUSE frame, allows a packet in the process of being transmitted to complete transmission prior to implementing the PAUSE. The MAC device is capable of generating MAC Control frames having any desired opcode. The parameter field associated with the MAC Control frame opcode is programmable. The destination address of the MAC Control frame is programmable. Automatic x-on/x-off is implemented. Flags may be set to enable/disable the IEEE 802.3x pause function in the MAC device and to override basic IEEE 802.3x operation in various ways.

Automatic MAC control frame generating apparatus for LAN flow control

In a 100BASE-T4 protocol network, the 'carrier.sub.-- status' signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Method and apparatus for using synthetic preamable signals to awaken

The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry. Pair swap is corrected by switching the signals received on the swapped pairs prior to transmission or repetition to subsequent circuitry. Link integrity status is indicated via a transmitted signal.

Apparatus and method for detecting and correcting pair swap, and

The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity by utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry. Pair swap is corrected by switching the signals received on the swapped pairs prior to transmission or repetition to subsequent circuitry. Link integrity status is indicated via a transmitted signal.

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San Jose, CA, United States of America

Eric T West