Cirrus Logic Inc.

Avnera Corporation

Silicon Laboratories Inc.

Eric T King

Douglas F Pastorello

Jianping Wen

Ali Hadiashar

David W Entrikin

Wai Lang Lee

Wai Laing Lee

Bruce Philip Del Signore

Garry Link

Michael Henderson Perrott

Amit Kumar

Patrick A Quinn

Xudong Zhao

Alexander C Stange

William Gardei

Frank Den Breejen

Adam C Broun

Victor Aguilar

Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Analog to digital converters with oversampling

A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Power supply for class G amplifier

A differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the PSRR of the amplifier. In another aspect of the present invention, a differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the CMRR of the amplifier. In a further aspect of the present invention, a Class D amplifier is provided with a passive differential feedback, summing with an input current at a differential virtual ground produced by an amplifier which is a sub-section of the Class D amplifier.

Calibrated feedback

A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable delay filtering permits the frequency detector to be less sensitive to data fluctuations, and random or pseudo random addition of jitter helps address low gain in the data stream. A VCO controller cycles through a number of control states and provides varying levels of gain, dither and delay during each of the control states.

Frequency detector including a variable delay filter

A slice and offset circuit is provided that uses a digital integrator in the feedback loop of the offset cancellation circuitry. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify the slice level, which is combined with a sensed offset level of the amplifier. The feedback loop includes a low pass filter that receives the combined signal indicative of the offset and the slice level. The low pass filter includes the digital integrator circuit that includes an up/down counter that counts in a direction determined according to a digital signal having a ones-density indicative of a value of the combined signal with respect to a reference signal, thereby generating a feedback signal that cancels offset and adjusts for slice.

Offset correction and slicing level adjustment for amplifier circuits

An energy-to-pulse (E2P) converter for converting analog voltage and current measurements into digital power consumption readout that has an improved output frequency range and can eliminate the potential information loss in a multiple-wires and multiple-phases power distribution system without added complex hardware. The E2P uses a threshold value T in determining the output pulse count which represents the energy/power consumption. The energy consumption E is updated every cycle of a first clock rate F during which a power P calculation is performed following a voltage V and a current I analog-to digital conversion. The updated energy consumption E is then divided by the threshold value T to determine the number of pulses that correspond to the power consumption. The number of pulses are output at a second clock rate F In so doing, more than one pulse can be generated for each P calculation thereby improving the output frequency range. To prevent complete signal overlaps that may lead to information loss in multiple-wires and multiple-phases power system, the pulse output for each wire can be programmed to have a different phase such that the pulses from the pulse outputs, which are all synchronous with each other, are non-overlapped.

Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing

An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase or wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Single phase bi-directional electrical measurement systems and methods using ADCs

Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC's.

Digital phase compensation methods and systems for a dual-channel analog-to-digital converter

Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I&minus;&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADCs.

Delay correction system and method for a voltage channel in a sampled data measurement system

A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.

High pass filtering with automatic phase equalization

A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

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Temple, NH, United States of America

Eric T King