Nvidia Corporation

Lucent Technologies Inc.

Hewlett-packard Development Company, L.p.

Alcatel-lucent USA Inc.

Sun Microsystems, Inc.

Cabletron Systems, Inc.

Hewlett-packard Development, L.p.

Acatel-lucent USA Inc.

Alcatel Lucent

Eric T Anderson

Philip Arnold Ferolito

Mike Morrison

Gregory S Mathews

Bryon S Nordquist

Joel James McCormack

Gunes Aybay

Shirish C Gadre

Lacky V Shah

Nirmal Raj Saxena

Brian Matthew Fahs

Nick Barrow-Williams

John Wilkes

Alexander Lev Minkin

Bendik Kleveland

Philip Payman Shirvani

Poornachandra Rao

James A Bauman

Peter Sommers

Jerome Francis Duluk, Jr

Henry Packard Moreton

John Stephen Montrym

Apurva Mehta

Emmett Michael Kilgariff

Jeffrey A Bolz

Cass Watson Everitt

Ira Cohen

Steven James Heinrich

Dirk Manfred Beyer

Alistair Veitch

Andrew J Tao

Janet Lynn Wiener

Terence Patrick Kelly

Jonathan J Dunaisky

J Arjun Prabhu

Yan Yan Tang

James Bauman

Ramesh Jandhyala

Ajay Gaonkar

Diwakar Tundlam

Mindong Chen

Robert J Schultz

Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.

Approach to reducing voltage noise in a stalled data pipeline

A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Approach to caching decoded texture data with variable dimensions

A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Technique for performing memory access operations via texture hardware

Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Load/store operations in texture hardware

A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

Technique for accessing content-addressable memory

A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.

Voltage droop reduction by delayed back-propagation of pipeline ready signal

A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

Determining a working set of texture maps

Techniques for graph data structure management. In one aspect, a data structure includes a plurality of nodes connected by edges. A node of the data structure includes a current set of variables for defining a state of the node and at least one last-in, first-out stack for storing pointers to prior sets of variables for the node. The state of the node may be saved by adding a pointer to at least one of the stacks at the node. The state of the node may be restored by removing the pointer from the stack and restoring the node variables to those indicated by the pointer. A first counter associated with a stack at the node may store a number of pending saves at the node, while a second counter may store a number of saves to be propagated to descendents of the node. A state of the data structure may be saved by traversing other nodes of the data structure and adding pointers or incrementing counters at the nodes.

Techniques for graph data structure management

A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.

Testing and error recovery across multiple switching fabrics

An embodiment of a method of dividing past computing instances into predictable and unpredictable sets begins with a first step of a computing entity storing a training data set comprising past computing instances. Each past computing instance comprises attributes and a past computing value. In a second step, the computing entity separates the training data set into a predictable set of past computing instances and an unpredictable set of past computing instances. According to an embodiment, a method of predicting a computing value begins with the first and second steps. The method of predicting the computing value continues with a third step of the computing entity forming a predictor from the predictable set of past computing instances. In a fourth step, the computing entity applies the predictor to a pending computing instance that meets a predictability test to determine a predicted value for the pending computing instance.

Method of dividing past computing instances into predictable and unpredictable sets and method of predicting computing value

A traffic forwarding system that uses a multicast start-of-packet (SOP) pointer to enqueue a multicast packet in packet queues. The system receives cells, assigns pointers to the cells, and stores the received cells in memory. The system assigns multicast SOP pointers to multicast SOP cells. The system reassembles cells into packets and enqueues the packets in packet queues for forwarding. A multicast packet is enqueued in a plurality of packet queues. The memory in which the multicast packet is stored is released after the multicast packet is dequeued from each of the plurality of packet queues.

Multicast packet queuing

A traffic control system and method with flow control aggregation. The system includes a switching fabric and an ingress module. The switching fabric includes read counters that are associated with a plurality of queues. The read counters represent an aggregated number of cells dequeued from respective queues since a previous flow control message (FCM) was sent to the ingress module. The read counters are reset when a FCM is created. The ingress module includes write counters that are associated with the queues. The write counters are incremented each time a cell is sent to the respective queues. The write counters are decremented in accordance with the FCM when the FCM is received. Also, read counters for one or more queues are aggregated into a single FCM.

Flow control in a distributed scalable, shared memory switching fabric system

A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Flexible multilevel output traffic control

Rate-limiting a traffic stream using a rate-limit hierarchy involves subjecting a packet to a first rate-limit check, the first rate-limit check corresponding to a first-level traffic classification, subjecting the packet to a second rate-limit check and an infinity rate-limit cheek, the second rate-limit check and the infinity rate-limit check corresponding to a second-level traffic classification, granting an automatic pass to the packet from the infinity rate-limit check regardless of whether or not the packet passes the second rate-limit check, and granting an overall pass of the rate-limit hierarchy if the packet passes the first rate-limit check. In an embodiment, the first-level traffic classification is a parent classification of the second-level traffic classification and the second-level traffic classification is a child classification of the first-level traffic classification.

Hierarchal rate-limiting at a network node that utilizes an infinity rate-limit check

Growing community of inventors

Palo Alto, CA, United States of America

Eric T Anderson