Nxp Usa, Inc.

Eric Simard

Xiao Sun

Yuan Li

A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) () having a processor () and a master device () having shared access to a single-port memory () by activating a timer () in a Performance Monitoring Unit (PMU) () to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter () in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.

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Kanata, Canada

Eric Simard