National Semiconductor Corporation

Eric Scheuerlein

Mehmet Aslan

Donald M Archer

An embodiment of the present invention is directed to a circuit for indicating the program status of an EPROM. The circuit includes a first and second transistor coupled to a first voltage potential. The circuit further includes a latching circuit coupled to the first and second transistors. The latching circuit outputs a first output value when the current through the first transistor is greater than the current through the second transistor and a second output value when less. The circuit further includes a capacitive element coupled between a gate of the first transistor and a third voltage potential, the capacitance of the capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM.

Known default data state EPROM

In a system for performing a dual mode single temperature trim upon an electronic device to remove combined mismatch and process variation errors, a dynamic element matching control is configured for enabling dynamic element matching of components of the electronic device. A process trim module is configured for performing a process trim to remove a temperature dependant error from the electronic device while the dynamic element matching is enabled within the electronic device. A mismatch trim module is configured for performing a mismatch trim to remove a mismatch error from the electronic device after the process trim has been performed. The mismatch trim is performed on a portion of the electronic device for which the dynamic element matching has been disabled. Additionally, the mismatch trim is performed at substantially an equivalent temperature to a temperature at which the process trim was performed.

Dual mode single temperature trimming

A circuit for creating a current complementary to absolute temperature comprises a first transistor and a second transistor. A resistor for generating a current complementary to absolute temperature has a first node coupled to the emitter of the first transistor and a second node coupled to the base of the first transistor. A first current mirror is coupled between the second node of the resistor and the emitter of the second transistor, the second transistor being used for replicating bias conditions of the first transistor. A second current mirror is coupled between the base of the first transistor and the base of the second transistor, and the second current mirror is used for canceling a base current of the first transistor.

Growing community of inventors

Los Gatos, CA, United States of America

Eric Scheuerlein