Ncr Corporation

Eric Sacher

Thomas E Trebelhorn

Robert G Fulks

Robert E Enfield

A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature file containing known correct signatures for the nodes of a board under test and also stores an image file which contains information defining the topology of the board under test. The driver/sensor circuits are programmable to receive test information generated by a test program stored in the main memory, transmit such information to inputs of a board under test, and receive information produced by the board under test in response to the input test information. The response received from outputs of the board under test is compared to a corresponding known-correct response to identify a faulty output of the board under test. The processor refers to the image file to identify a logic element driving the faulty output and to identify the nodes which are inputs to the logic element. The processor causes instructions to be displayed to the operator of the portable digital tester to instruct the operator to probe the input nodes of the logic element. A signature is generated for each node and compared to a corresponding known correct signature for that node as it is probed by the operator to identify a faulty input node. For each faulty node found, the measured signature, the initial state, and a number equal to the smaller of an input test number of the known correct initial transition of the faulty node and an input test number of the first incorrect transition of the faulty node is stored in a history file having pointers to the image file for each node. If a component is found having a faulty output and all good inputs, that component is identified as defective. If a loop is identified by the main processor, the operator is instructed to test all external inputs to the loop; if a faulty external input is found, the loop is resolved, and the processor instructs the operator to probe another node. If the external inputs are all good, the main processor scans the history table to determine which node in the loop failed first and indicates that the component driving that node is the probable fault.

Method and apparatus for isolating faults in a logic circuit

A program is developed for testing printed circuit boards by applying a proposed test program to a board which is initially in an arbitrary response state, comparing the resulting response pattern with a reference, modifying the proposed program if necessary to obtain a valid comparison, running the program on the board successively while faults are applied to selective board input nodes, determining penetration of the faults through the board by analyzing the toggle signatures of the response nodes, and again modifying the program if necessary. Circuit boards are tested with the resulting program by accumulating a running toggle signature number for selected response nodes as the program is applied to the test board, periodically sampling the numbers, and comparing the test samples with corresponding samples from a reference board. Defective board devices can then be traced and remedied; if a sampled defect persists, the test program is advanced in single step increments from the preceding sample until the defect is again detected. The board connections to the defective node may then be analyzed to pinpoint the defect. The invention also includes apparatus for performing the above method with a programmed data processing means and data storage devices.

Method and apparatus for testing printed circuit boards

The present invention relates to apparatus and method for testing logic circuit boards for complex logical faults contained therein. A known good identical logic circuit is stimulated by a preselected sequence of binary test patterns and the number of transitions in logical state before achieving a final logical state as well as the final logical state for a number of points within the circuit are monitored and saved. The logic circuit being tested is then stimulated by the same test pattern sequence and the number of transitions and final logical states achieved are compared. Failure to have identity between the known good logical circuit and the logical circuit being tested both as to number of transitions and final logical state achieved for the tested points indicates a malfunction within the board which would not be detected by mere sampling of the final output state alone.

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Phoenix, AZ, United States of America

Eric Sacher