Globalfoundries Inc.

Eric S Parent

Wolfgang Sauter

David Brian Stone

Nicholas A Polomoff

Mark William Kuemerle

Eric W Tremble

Seungman Choi

Liang Cao

Jie Zhang

David N Power

Jawahar P Nayak

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

Methods according to the disclosure include: predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts; identifying actual PSGs in a circuit manufactured using the proposed IC layout; determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct; in response to the predicting being incorrect: adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and flagging the proposed IC layout as incorrectly predicted; and in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.

Prediction of process-sensitive geometries with machine learning

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Saratoga Springs, NY, United States of America

Eric S Parent