Intel Corporation

Eric S Gayles

Bruce Querbach

David G Ellis

Amjad M Khan

Eshwar Gollapudi

Bharat Bhushan

Jay Joseph Nejedlo

Sean R Babcock

Michael J Tripp

Debashree Ghosh

A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Automatic self test of an integrated circuit component via AC I/O loopback

A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Push button mode automatic pattern switching for interconnect built-in self test

A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

Contention-free, low clock load domino circuit topology

Data enabled complex logic gates provide improved speed/power performance over conventional topologies such as static logic or clocked domino logic. Within a data enabled complex logic gate, complementary parallel logic structures, such as NFET logic trees, are configured such that for any combination of input variables one logic structure will produce a logic low as an output and the other logic structure will produce a logic high as an output. The logic structures are cross-coupled to each other by way of internal precharge devices, and are further individually coupled to an output latch. In this way the logic structures can be precharged to prepare for evaluation of the next set of input signals while the output latch maintains the result of the previous evaluation. In a further aspect of the invention, data enabled complex logic gates are combined with pass gate latches and multiplexer based logic gates to produce a high-speed, low-power logic pipeline.

Data enabled logic circuits

A logic device that allows the implementation of a fast-switching logic gate is described. One implementation of the logic device includes an output node and a reference node electrically isolated from one another by a transmission gate. During a first period of time, the nodes are charged to complementary logic levels. During a second period of time, the transmission gate is enabled, allowing the charge on the nodes to be redistributed. A pair of complementary input terminals are connected to the reference and output nodes, such that if the input terminal connected to the output node is at the same logic level as the output node during the first period, then the voltage level of the output node is pulled back from its redistributed state to its original state. However, if the input terminal voltage level to the output node is the complement of the original voltage level of the output node, then a charge/discharge circuit is enabled to pull the output node to a voltage level that is a complement to its original voltage level.

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Folsom, CA, United States of America

Eric S Gayles