Spin Memory, Inc.

Spin Transfer Technologies, Inc.

Integrated Silicon Solution, (cayman) Inc.

Eric Ryan

Marcin Gajek

Kadriye Deniz Bozdag

Michail Tzoufras

Kuk-Hwan Kim

Dafna Beery

Satoru Araki

Andrew J Walker

Mourad El Baraji

Davide Guarisco

Andy Walker

Girish Jagtiani

Mustafa Pinarbasi

Amitay Levi

Gian Sharma

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Patterned silicide structures and methods of manufacture

A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.

Method for manufacturing a data recording system utilizing heterogeneous magnetic tunnel junction types in a single chip

An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.

Systems and methods utilizing serial and parallel configurations of magnetic memory devices

A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSior CoSiand also causes the underlying amorphous silicon to crystallize.

High density MRAM integration

A magnetic memory device that includes magnetic read elements and magnetic reference cells. The magnetic reference cells include magnetic tunnel junction elements having the same construction as the magnetic read elements. The reference cells produce a reference signal that can be compared with a read signal from the magnetic read element to determine whether the read element is in a high or low resistance state. During creation of the reference signal, the current passes in such a way so that reference cells are forced to be in the right state while causing no disturbance to the reference cell. The reference cell includes magnetic tunnel junction elements and also includes circuitry configured to produce a magnetic field that biases the magnetic tunnel junction elements of the reference cell into a desired magnetic state to ensure that the desired magnetic state of the reference cell magnetic tunnel junction elements is maintained.

MRAM array having reference cell structure and circuitry that reinforces reference states by induced magnetic field

A magnetic data recording system utilizing different magnetic memory element types to optimize competing performance parameters in a common memory chip. The memory system includes a first memory portion which can be a main memory and which includes magnetic memory elements of a first type, and a second memory region which can be a temporary memory region and which includes magnetic memory elements of a second type. A memory controller can be provided for controlling the input and retrieval of data to and from the first and second memory elements. The second, memory region can be a scratchpad memory or could also be cache type memory. The first type of magnetic memory elements can be designed for high data retention, whereas the second type of magnetic memory elements can be designed for fast write speed (low latency) and low write power consumption.

Memory system utilizing heterogeneous magnetic tunnel junction types in a single chip

A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.

Methods and systems for writing to magnetic memory devices utilizing alternating current

The various implementations described herein include methods, devices, and systems for fabricating magnetic memory devices. In one aspect, a method of fabricating a magnetic memory device includes: (1) providing a dielectric substrate with a metallic core protruding from the dielectric substrate, where: (a) a first portion of the metallic core is surrounded by the dielectric substrate and a second portion of the metallic core protrudes away from a surface of the dielectric substrate; and (b) the second portion includes: (i) a surface offset from the surface of the dielectric substrate and (ii) sidewalls extending away from the surface of the dielectric substrate to the offset surface; (2) depositing a first ferromagnetic layer on exposed surfaces of the metallic core and the dielectric substrate; (3) depositing a spacer layer on exposed surfaces of the first ferromagnetic layer; and (4) depositing a second ferromagnetic layer on exposed surfaces of the spacer layer.

Methods of fabricating three-dimensional magnetic memory devices

A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSior CoSiand also causes the underlying amorphous silicon to crystallize.

A magnetic memory device is provided. The magnetic memory device includes: (i) a cylindrical core, (ii) a first cylindrical ferromagnetic layer that surrounds the cylindrical core, (iii) a spacer layer that surrounds the first cylindrical ferromagnetic layer, and (iv) a second cylindrical ferromagnetic layer that surrounds the spacer layer. The cylindrical core, the first cylindrical ferromagnetic layer, the spacer layer, and the second cylindrical ferromagnetic layer collectively form a magnetic tunnel junction.

Three-dimensional magnetic memory devices

A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.

Perpendicular magnetic tunnel junction memory cells having shared source contacts

A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.

Method for manufacturing a magnetic memory element array using high angle side etch to open top electrical contact

A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Systems and methods utilizing serial configurations of magnetic memory devices

A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.

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Fremont, CA, United States of America

Eric Ryan