Texas Instruments Corporation

Eric Robert Hansen

Denis R Beaudoin

Chunhua Hu

Venkateswar Reddy Kowkutla

Thomas Anton Leyrer

Krishnan Sridhar

Karl M Guttag

Iain Craig Robertson

James G Bearss

Herman W Harrison

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect 'OSI' model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network

A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.

Resource allocation in a multi-processor system

Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network

This invention comprises a converged printer architecture for controlling both electro-photographic (EP) processing and raster image processing (RIP) of data for laser modulation over a video line. By converging EP process control with image processing control, significant advantages in cost, image quality, and output stability are achieved. A digital signal processor (DSP) serves as the central processing resource of the architecture. The DSP is well suited for the dual role of image processing and real-time feedback process control. The DSP can operate in open loop motor/motion control, print process control, and in closed loop feedback control including image processing adaptations for quality and stability enhancements.

Integrated raster image processor and electro-photographic engine controller

A printer controller for processing print data includes a data processor, direct memory access controller, first and second memories with corresponding first and second transfer data busses. A bus switch selectively connects the first and second data transfer busses. When uncoupled, the data processor accessed the said first memory via the first data transfer bus and the direct memory access controller may independently accesses the second memory via the second data transfer bus. When connected, either the data processor or the direct memory access controller may access either memory to the exclusion of the other. This permits better allocation of data transfer bandwidth in the memory controller.

Shared memory architecture for increased bandwidth in a printer controller

A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level. The priority level for each cache entry may be recalled from a cache priority level look-up table or entered from an instruction via coding in opcode bits or a priority setting instruction. In an alternative embodiment this technique is used with a memory configuration cache storing memory access parameters for corresponding address ranges enabling adaption to plural memories requiring differing sets of memory access parameters.

Growing community of inventors

McKinney, TX, United States of America

Eric Robert Hansen