International Business Machines Corporation

Eric Raymond Evarts

Virat Vasav Mehta

Alexander Reznicek

Pouya Hashemi

Michael Rizzolo

Heng Wu

Chandrasekharan Kothandaraman

Karthik Yogendra

Saba Zare

Krishna Thangaraj

Bahman Hekmatshoartabari

Robert Russell Robison

Oscar Van Der Straten

Xuefeng Liu

Ashim Dutta

Gauri V Karve

Praveen Joseph

Embodiments are disclosed for a system that includes a data scrubbing circuit, a magnetoresistive random access memory (MRAM) having a memory array, and an analog persistent vital information circuit (APVIC) that performs a method. The method includes resetting weights corresponding to blocks of the memory array. The method further includes adjusting the weights based on a timer, data accesses on the memory blocks, and weight change values corresponding to the weights. The method also includes determining, in response to the timer, a data scrubbing threshold based on ambient temperature and magnetic field strength. The method additionally includes determining one of the weights meets the data scrubbing threshold. Further, the method includes providing, in response to the determination, an indication that a data scrubber, scrub one of the memory blocks corresponding to the weight that meets the data scrubbing threshold. Also, the method includes resetting the weight.

Magnetoresistive random access memory with data scrubbing

A memory system for storage access monitoring is provided. The memory system includes a media controller of a memory. An analog persistent circuit is coupled to the media controller and configured to monitor access to the memory. The analog persistent circuit stores persistent data related to memory access counts access signals from the command/address bus. A command/address bus is coupled to the analog persistent circuit. A memory array is communicatively coupled to the command address and the media controller.

Analog persistent circuit for storage access monitoring

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

Selectively biasing magnetoresistive random-access memory cells

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

Spin-orbit-torque magnetoresistive random-access memory

An embodiment of the invention may include a magnetic random-access memory (MRAM) structure and method of making the structure. The MRAM structure may include a magnetic tunnel junction stack. The MRAM structure may include a magnetic liner located between the magnetic tunnel junction stack and a top contact, where the magnetic liner may be a ferromagnetic material. This may enable the magnetic liner to act as an independent variable to balance many of the magnetic parameters in the MTJ film stack in order to achieve zero magnetic field at the MTJ layer.

MRAM containing magnetic top contact

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.

Two-bit magnetoresistive random-access memory cell

A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.

Two-bit magnetoresistive random-access memory device architecture

A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.

Magnetoresistive random-access memory device including magnetic tunnel junctions

A sub-micrometer pressure sensor is provided that includes a multilayered magnetic tunnel junction (MTJ) pillar that contains a non-magnetic metallic spacer separating a first magnetic free layer from a second magnetic free layer. The presence of the non-magnetic metallic spacer in the multilayered MTJ pillar improves the sensitivity without compromising area, and makes the pressure sensor binary (either 'on' or 'off') with little or no drift, and sensitivity change over time. Moreover, the resistivity switch in such a pressure sensor is instantly and a low error rate is observed.

Multilayered magnetic free layer structure in magnetic tunnel junction arrays for sub-micrometer resolution pressure sensors

An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.

Nanosecond non-destructively erasable magnetoresistive random-access memory

A sub-micrometer pressure sensor including a multilayered magnetic tunnel junction (MTJ) pillar containing a magnetostrictive material layer above or below a magnetic free layer of the multilayered MTJ pillar is provided. Advanced patterning allows for scaling of the multilayered MTJ pillar down to 25 nm or below which enables the formation of a large array of extremely high resolution pressure sensors. By varying the thickness of the magnetostrictive material layer, the sensitivity of the pressure sensor can be fine tuned. Unique magnetostrictive materials in the multilayered MTJ pillar will alter the device current with the input of external pressure. Furthermore, unique arrays with much smaller critical elements can be organized in differential sensing arrangements of the multilayered MTJ pillar with pressure sensing capability that can outperform current piezoelectric based pressure sensing arrays.

Nanoscale magnetic tunnel junction arrays for sub-micrometer resolution pressure sensor

A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

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Eric Raymond Evarts