Intel Corporation

Eric R Wehage

David M Lee

David J Harriman

Jasmin Ajanovic

Blaise B Fanning

Buck Gremel

Wayne Moore

Ken Creta

Vincent J Zimmer

Debendra Das Sharma

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Ravishankar Iyer

Andrew J Herdrich

Mallik Bulusu

Robert Charles Swanson

Yen-Cheng Liu

Sridhar Muthrasanallur

Stephen R Van Doren

Stephen T Palermo

Edwin Verplanke

Rupin H Vakharwala

Julius Yuli Mandelblat

Jeffrey D Chamberlain

Toshiyuki Sakuta

Annie Foong

Bryan E Veal

Kersi H Vakil

Jayakrishna P S

Anne Meixner

Michael J Greger

K L Siva Prasad Gadey Nv

Samit Mehrotra

Kyle T McCanta

Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms

An apparatus is provided which comprises: an input/output (I/O) port; a first circuitry to update an in-band presence detect field, based on communication via an in-band channel; a second circuitry to update an out-of-band presence detect field, based on communication via an out-of-band channel; and a third circuitry to update a presence detect state change field, wherein the third circuitry is to selectively ignore the out-of-band presence detect field and utilize the in-band presence detect field, while the third circuitry is to update the presence detect state change field.

Managing surprise hot plug in low power state

Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space.

Method, device and system for aggregation of shared address devices

Methods and apparatus to protect segments of memory are disclosed herein. An example method includes intercepting an interrupt request indicating an error; determining whether a first segment of memory is corrupt, the first segment of memory being designated as a protected region of memory; when the protected region of memory is corrupt, repairing the corrupted region of memory using a parity block of code; and in response to validating the protected region of memory, generating an interrupt enabling a utilization of code stored in the protected region of memory to handle the error associated with the interrupt request.

Methods and apparatus to protect segments of memory

A method and system of error recovery of a device attached to a platform without requiring a system reset. In one embodiment of the invention, a platform detects an error(s) of an attached device and shuts down the communication link with the attached device. The platform corrects the error(s) and automatically re-trains the communication link with the attached device. In this way, no reset of the platform is required to correct the detected error(s) in one embodiment of the invention.

Method and system of live error recovery

An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.

General input/output architecture, protocol and related methods to manage data integrity

An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.

A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.

Leakage testing for differential signal transceiver

A system and method for creating a built-in self-testing (BIST) state machine to test random access memories (RAMs) are disclosed. The BIST state machine can be simplified to a simple four-state state machine while accommodating a large group of test suites by programming each state to have the capability of performing one of four necessary operations. These operations include a write operation, a read operation, a read/write operation and a null operation. Further bits and signals can be added to the state machine to enable an even larger array of test suites to be performed.

Low cost built-in self test state machine for general purpose RAM testing

A method and apparatus for a configuration ring is described. The method and apparatus include a configuration ring including a master, a first target, and a second target, the master coupled to the first target through a ring, the first target coupled to the second target through the ring, and the second target coupled to the master through the ring. The method and apparatus also include a method of using the configuration ring including originating a packet, passing the packet, decoding the packet, and utilizing the packet. The method and apparatus also includes a system including a processor, and processor bus coupled to the processor, a data chip coupled to the processor bus, a address chip coupled to the processor bus and the data chip, the address chip having a configuration ring, the configuration ring having a master, a first target and a second target, the master coupled through a ring to the first target, the first target coupled through the ring to the second target, the second target coupled through the ring to the master.

Method and apparatus for a configuration ring

A local integrated circuit device provides remote configuration access to one or more remote integrated circuit devices. The local integrated circuit device receives configuration access requests through at least two interfaces. The local integrated circuit device accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.

Remote configuration access for integrated circuit devices

Growing community of inventors

Tenino, WA, United States of America

Eric R Wehage