Intel Corporation

Eric R Heit

Varghese George

Sanjeev S Jahagirdar

Jose P Allarey

Avinash N Ananthakrishnan

Jeremy J Shrall

Anupama Suryanarayanan

Ameya Ambardekar

Joseph M Alberts

Craig Topper

Glenn J Hinton

Stephen Anthony Fischer

Patrice L Roussel

Gerald Bennett

Vladimir Pentovski

In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.

Processor to pre-empt voltage ramps for exit latency reductions

Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.

Method, apparatus and system to dynamically choose an optimum power state

Method, apparatus and system to dynamically choose an aoptimum power state

The present invention discloses a method and apparatus for matching data types of operands in an instruction. A type code of an operand used by the instruction is determined. An attribute value of a storage element which corresponds to the operand is read from a speculative array. This attribute value is then compared with the type code.

Checking data type of operands specified by an instruction using attributes in a tagged array architecture

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Hillsboro, OR, United States of America

Eric R Heit