Intel Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Eric R Delano

Akhilesh Kumar

Ioannis T Schoinas

Jose Andy Vargas

Mani Ayyar

Ganesh Kumar

Adrian C Moga

Ren Wang

Herbert H Hum

Donald Charles Soltis, Jr

Eric J DeHaemer

Kevin Safford

Zeshan A Chishti

James R Vash

Brinda Ganesh

Leena K Puthiyedath

Richard Lawrence Carlson

David Bubien

Michelle M Sebot

Scott J Erlanger

Jay Jayasimha

Christian Maciocco

William R Bryg

Rohit Bhatia

Doddaballapur N Jayasimha

Ahmad A Samih

Tsung-Yuan Charlie Tai

Dheemanth Nagaraj

Gregory S Averill

Pinkesh J Shah

Vincent R Freytag

Christopher L Lyles

Yen-Cheng Liu

Dale Calvin Morris

Jonathan Kent Ross

Aamer Jaleel

Bongjin Jung

Shawn Kenneth Walker

Michael Kennard Tayler

Kenneth K Chan

John F Shelton

James R Callister

Mark M Gibson

Craig A Gleason

Mark A Forsyth

Michael A Buckley

Ioannis Yannis Schoinas

Gregory D Burroughs

Doddaballapur Narasimha-Murthy Jayasimha

Steven W LaMar

Gordon Kurpanek

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Method, system, and apparatus for dynamic reconfiguration of resources

In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

Virtual shared cache mechanism in a processing device

In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Power gating a portion of a cache memory

Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.

Memory mirroring and migration at home agent

Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

Home agent data and memory management

Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Mitigating context switch cache miss penalty

Provided is a system to communicate data in a computing environment, comprising an interleaving mechanism operable to interleave data being communicated across the computing environment according to a selected interleaving protocol; and an interleaving instruction set operable on the interleaving mechanism providing operating instructions to the interleaving mechanism in accordance with the selected interleaving protocol wherein the data can be interleaved between one or more data channels of the computing environment and within one or more data channels of the computing environment.

Interleave mechanism for a computing environment

Growing community of inventors

Ft. Collins, CO, United States of America

Eric R Delano