Mbda UK Limited

Matra Bae Dynamics (uk) Limited

Eric R Campbell

Hugo R Simpson

An integrated circuit (A) for multitasking support for processing unit (A) holds control variables for each task (or activity) to run on its associated processor (A) and identifies the next task that should run. The circuit (A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of 'tiles', each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Integrated circuits for multi-tasking support in single or multiple processor networks

A transparent latch, having a signal input D, an output Q and a control input C for selecting one of two operating modes, functions by either allowing the output to follow the input (in an enable mode) or by blocking any subsequent changes in input signal level (in an inhibit mode). Owing to the design of the latch, relative propagation delays through gates and interconnecting wires cannot cause a wrong value to be latched, this being in contrast with known arrangements. Therefore constraints on the physical layout of the latch are removed. In one embodiment the latch comprises two pairs of NAND gates (,) each pair being connected in a feedback configuration.

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Hertfordshire, United Kingdom

Eric R Campbell