Texas Instruments Corporation

Eric Ponsot

Gilbert Laurenti

Mark L Buser

Shigeshi Abiko

Douglas E Deao

Jean-Pierre Giacalone

Marc Couvrat

Eric L Badi

Armelle Laine

Herve Catan

Karim Djafarian

Vincent Gillet

Alain Boyadjian

Gael Clave

Jean-Marc Philippe Bachot

Francois Theodorou

Anne Lombardot

Yves Masse

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Laurent Ichard

Emmanuel Ego

Frederic Nidegger

David Russell

N M Ganesh

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width ( ) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats ( ) are combined with non-operational instructions (NOP, NOP ) to form a large number of combination instructions that match any instruction length format.

Various length software breakpoint in a delay slot

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Vence, France

Eric Ponsot