Infineon Technologies Ag

Eric Pihet

Thorsten Hinderer

Maximilian Mangst

David Astrom

Jens Repp

Josef Gerner

Christian Cornelius Russ

Alexander Zeh

Rudolf Zelsacher

Magnus-Maria Hell

Ordwin Haase

Dieter Metzner

Gabriel-Dumitru Cretu

Filippo Magrini

Bernhard Stein

Tobias Islinger

Michael Glavanovics

Vivin Richards Allimuthu Elavarasu

Thomas Krotscheck

An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

ESD protection circuit

A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

Field bus driver circuit

In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Bus transceiver

A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.

Transceiver and transceiver systems

A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.

Interface circuit

Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

Differential bus receiver with four-quadrant input circuit

A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal.

Semiconductor device chip package with electronic switching using dedicated ground pin coupled to a virtual ground node

According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.

System and method for a low emission network

A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.

Driver circuit for a two-wire conductor and method for generating two output currents for a two-wire conductor

The invention relates to a method for monitoring a microcontroller having at least one normal operating state and one state with a reduced power consumption and to a circuit configuration for carrying out the method. The method enables the functionality of the microcontroller to be monitored even in the state with the reduced power consumption. The method includes steps of: during the normal operating state, receiving a status signal having pulses from the microcontroller and resetting the microcontroller if the pulses are not received within a predefined time pattern; and during the state with the reduced power consumption, transmitting a wakeup signal having a sequence of pulses to the microcontroller, and resetting the microcontroller if there is no confirmation by the microcontroller within a predefined time interval after a pulse of the wakeup signal.

Circuit configuration and method for monitoring a micro-controller

A circuit configuration provides an output voltage from an input voltage. The circuit configuration has a voltage regulator with an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and drive input for receiving a drive signal. A drive circuit is coupled to the drive input and switches the voltage regulator on and off in a clocked manner according to a state signal.

Output level responsive switching on/off of a linear regulator

A temperature sensor for a MOS circuit configuration is implemented as the gate of a MOS transistor and configured as a two-terminal network with a gate input and a gate output. By measuring the voltage drop across gate it is possible to determine the temperature at its location.

Temperature sensor for a MOS circuit configuration

A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an antiphase signal using a two-wire line. A control circuit is connected to one of the driver paths and controls the turn-on resistance of the power transistor circuit in this driver path such that the power transistor circuits in the two driver paths have the same turn-on resistance.

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Munich, Germany

Eric Pihet