Tektronix, Inc.

Avnera Corporation

Eric P Etheridge

Victor Lee Hansen

Samuel J Peters, Ii

Alexander C Stange

Amit Kumar

Eric Sorensen

Shankar Rathoud

Roy I Siegel

Kevin Thomas Ivers

Mike Wurtz

Daniel G Knierim

Gordon W Shank

Forrest A Edwards

Michael Jon Wurtz

Paul M Gerlach

Grigory Kogan

Dawn Gayle Flakne

David J McKinney

George S Walker

Thuy T Nguyen

Kayla R Klingman

Victor Lee Hanson

Spiro Sassalos

Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

Headphone off-ear detection

A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a 'toothless' clock signal, wherein the sample counter is configured to be decremented by the 'toothless' clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the &#x201c;toothless&#x201d; clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.

SPDIF clock and data recovery with sample rate converter

A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a 'toothless' clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the 'toothless' clock signal to the sample rate converter.

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

A method and apparatus for rasterizing a digital sample stream by producing histograms for each of a plurality of time slices forming a display frame. Time slice histograms for at least one display frame are stored in a circular memory buffer and provided to a display raster for display. The first time slice displayed optionally comprises that time slice temporally associated with a trigger condition.

Architecture providing increased information display for long acquisitions or constrained memory bandwidth

The subject invention addresses the problem of aliasing in subsampled data by adding dither to the timing of the subsampling of the data. The subject invention solves a speed problem caused by delays in modifying (i.e., dithering) the A/D converter sampling clock. It is herein recognized that to maintain a high acquisition rate one should randomly select (i.e., dither) samples after demultiplexing the data into a wider and slower stream of samples, rather than attempting to modify the high speed A/D converter sampling clock.

Dithering apparatus to properly represent aliased signals for high speed signal sampling

A new oscilloscope design improves the processing of acquired voltage-versus-time data through the efficient high speed acquisition and rasterization of such data into a form that includes multiple-bits-per-pixel intensity information. The multi-bit-per-pixel variable intensity rasterizer is optimized for maximum throughput and most efficient use of memory bandwidth. In the presence of faltering trigger rates, rasterization interruption provides a high probability of capturing the data associated with the slow triggers. Circuitry is provided to compensate for acquisition time and amplitude non-linearities. Many-bits-per-pixel intensity information is mapped into a fewer-bits-per-pixel format by a controllable transfer function that provides multiple viewing capabilities for the operator. Another mode of operation emphasizes infrequent events over commonly occurring ones using variations in brightness or color.

Compression and acquisition count optimization in a digital oscilloscope variable intensity rasterizer

High waveform throughput digital oscilloscope with variable intensity rasterizer and variable intensity or color display

Emphasizing infrequent events in a digital oscilloscope having variable intensity rasterizer and variable intensity or color display

High probability capture of slow trigger rate acquisitions in a digital oscilloscope with variable intensity rasterization

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Beaverton, OR, United States of America

Eric P Etheridge