Analog Devices,inc.

Eric Otte

Carroll Clifton Speir

Nevena Rakuljic

Jeffrey Paul Bray

Siddharth Devarajan

Corey Petersen

Carroll C Speir

An ADC can include a plurality of time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC can have interleaving errors, since the time-interleaved ADCs in the ADC are not always perfectly matched. One way to calibrate for these mismatches is by observing the digital output signals of the time-interleaved ADCs in the background, or more broadly, without knowledge of the input signal to the ADC (often referred to as 'blind' calibration). Due to the nature of these calibrations, the performance of the calibration would significantly degrade when the input signal has certain problematic input conditions, such as a certain coherent input frequency. To address this issue, the data being used for calibration of interleaving errors can go through a qualifying process to assess whether to update error estimates based on the data.

Histogram-based qualification of data used in background or blind calibration of interleaving errors of time-interleaved ADCS

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Signal path linearization

A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

Data handoff between randomized clock domain to fixed clock domain

Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

Measuring and correcting non-idealities of a system

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

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Eric Otte