International Business Machines Corporation

Microsoft Technology Licensing, LLC

Eric Oliver Mejdrich

Robert Allen Shearer

Paul E Schardt

Russell Dean Hoover

Matthew Ray Tubbs

Adam James Muff

Jeffrey Douglas Brown

Jamie Randall Kuesel

Jon K Kriegel

Miguel Comparan

David Arnold Luick

David Keith Fowler

Sandra S Woodward

Giora Biran

Clarence Rosser Ogilvie

Robert Allen Drehmel

Mark Gary Kupferschmidt

Charles S Woodruff

Mark E Kautzman

Ming-i Mark Lin

Ling Tony Chen

Bruce Leroy Beukema

Robert Spencer Horton

Jonathan E Lange

John Victor Sell

Brian Lee Koehler

Corey Virgil Swenson

Bruce Marshall Walk

Mark Owen Maxson

Kenneth Michael Valk

Charles David Wait

Timothy Hume Heil

J Andrew Goossen

James Anthony Marcella

Mark Joseph Hickey

Gregory Mayo Daly

Jeffrey Andrews

Nicholas Robert Baker

Peter Anthony Atkinson

Frederick Jacob Ziegler

Alfred T Watson, Iii

Jay Shih Tsao

Alfred Thomas Watson, Iii

James Adam Hunter

Michael Grassi

Brent Francis Hilgart

Dave Fowler

Matthew Adam Cushing

Allen James Gavin

John V Sell

Disclosed herein is a modular computing device that provides a user options to upgrade an existing computing device as improved expansion units become available without rendering the underlying base unit obsolete. The base unit of the modular computing device receives high-voltage AC power and one or more power supplies within the base unit converts the AC power to low-voltage DC power that is consumed within the base unit. An AC power transfer unit transfers AC power from the base unit to an expansion unit installed within an expansion dock of the base unit. One or more power supplies within the expansion unit convert the received AC power to low-voltage DC power that is consumed within the expansion unit.

Modular computing device with common AC power

The subject disclosure is directed towards using one or more of hardware, a hypervisor, and privileged mode code to prevent system mode code from accessing user mode data and/or running user mode code at the system privilege level, or vice-versa. Also described is (in systems with a hypervisor) preventing non-hypervisor code from running in hypervisor mode or accessing hypervisor-only data, or vice-versa. A register maintained by hardware, hypervisor, or system mode code contains data access and execution polices for different chunks of addressable space with respect to which requesting entities (hypervisor mode code, system mode code, user mode code) have access to or can execute code in a given chunk. When a request to execute code or access data with respect to an address is received, the request is processed to determine to which chunk the address corresponds. The policy for that chunk is evaluated to determine whether to allow or deny the request.

Secure privilege level execution and access protection

A circuit arrangement, program product and method are provided for resetting a dynamically grown Accelerated Data Structure (ADS) used in image processing in which an ADS is initialized by reusing the root node of a prior ADS and resetting at least one node in the prior ADS to break a link between the reset node and a linked-to node in the prior ADS. By doing so, the memory allocated to the prior ADS may be reused for the new ADS, without having to clear or wipe out all of the allocated memory. In addition, in some instances, given the similarity of many image frames, often some or all of the node structure of a prior ADS may be reused for a new ADS, requiring only the contents of nodes to be cleared, instead of having to clear out all of the nodes in the prior ADS. As a result, the processing overhead associated with initializing a new ADS can be significantly reduced.

Resetting of dynamically grown accelerated data structure

The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a cross product. The permute instructions may be dependent on one another and may require the use of temporary registers. Embodiments of the invention provide a permute instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby reducing the number of instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.

Single precision vector permute immediate with 'word' vector write mask

A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is partially or completely flushed as a result of an instruction redirect (e.g., due to a branch mispredict), instructions can be forwarded to subsequent stages in an instruction unit and/or to one or more execution units without the latency associated with passing through the instruction buffer.

Instruction buffer bypass of target instruction in response to partial flush

A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.

Accelerated data structure positioning based upon view orientation

An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.

External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit

By mapping leaf nodes of a spatial index to processing elements, efficient distribution of workload in an image processing system may be achieved. In addition, processing elements may use a thread table to redistribute workload from processing elements which are experiencing an increased workload to processing elements which may be idle. Furthermore, the workload experienced by processing elements may be monitored in order to determine if workload is balanced. Periodically the leaf nodes for which processing elements are responsible may be remapped in response to a detected imbalance in workload. By monitoring the workload experienced by the processing elements and remapping leaf nodes to different processing elements in response to unbalanced workload, efficient distribution of workload may be maintained. Efficient distribution of workload may improve the performance of the image processing system.

Dynamic spatial index remapping for optimal aggregate performance

Memory sharing in a software pipeline on a network on chip ('NOC'), the NOC including integrated processor ('IP') blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.

Software pipelining on a network on chip

Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.

Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline

A circuit arrangement, program product and circuit arrangement render stereoscopic images in a multithreaded rendering software pipeline using first and second rendering channels respectively configured to render left and right views for the stereoscopic image. Separate transformations are applied to received vertex data to generate transformed vertex data for use by each of the first and second rendering channels in rendering the left and right views for the stereoscopic image.

Rendering of stereoscopic images with multithreaded rendering software pipeline

Data processing on a network on chip ('NOC') that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output ('I/O') accelerator that administers at least some data communications traffic to and from the at least one IP block.

Network on chip with an I/O accelerator

Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.

DMA-based acceleration of command push buffer between host and target devices

An apparatus, program product and method reuse static image data generated during rasterization of static geometry to reduce the processing overhead associated with rasterizing subsequent image frames. In particular, static image data generated one frame may be reused in a subsequent image frame such that the subsequent image frame is generated without having to re-rasterize the static geometry from the scene, i.e., with only the dynamic geometry rasterized. The resulting image frame includes dynamic image data generated as a result of rasterizing the dynamic geometry during that image frame, and static image data generated as a result of rasterizing the static image data during a prior image frame.

Reuse of static image data from prior image frames to reduce rasterization requirements

Growing community of inventors

Rochester, MN, United States of America

Eric Oliver Mejdrich