Cadence Design Systems, Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Inc.

Solbrae, Inc.

Eric Nequist

Richard Brashears

Javier A DeLaCruz

Steven L Teig

Ilyas Mohammed

Michael McSherry

Matthew A Liberty

David Allan White

Steven Lee Pucci

Jeffrey Scott Salowe

David Cross

Laura Wills Mirkarimi

Kenneth Duong

Jung Ko

Roland Ruehl

Robert L Brashears

Greg C Buchner

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

3D chip with shared clock distribution network

An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.

Systems and methods for inter-die block level design

Face-to-face mounted IC dies with orthogonal top interconnect layers

3D chip sharing power circuit

3D chip sharing clock interconnect layer

Disclosed is an improved method, system, and mechanism for a reader mechanism for a container-based approach for monitoring the history and/or quality of a consumable product. According to one approach, a monitoring mechanism is affixed to a wine container (e.g., a wine bottle) to monitor the handling/storage history and/or the drinkability of the wine inside the container. One or more environmental sensors are associated with the monitoring mechanism which tracks environmental conditions that may affect the wine. The tracked environmental conditions are analyzed to determine and/or indicate the drinkability of the wine. A reader mechanism is used to access and/or control the monitoring mechanism.

Mechanism and method to implement a reader mechanism for a container-based monitor of a consumable product

An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Method and mechanism for implementing extraction for an integrated circuit design

A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Method and mechanism for identifying and tracking shape connectivity

Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Method and system for implementing efficient locking to facilitate parallel processing of IC designs

Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.

Method and system for model-based routing of an integrated circuit

An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.

Method, system, and computer program product for improved electrical analysis

Growing community of inventors

Monte Sereno, CA, United States of America

Eric Nequist