Blue Cheetah Analog Design, Inc.

Other

G-2 Networks, Inc.

Eric Naviasky

Elad Alon

William Pierce Evans

Hao Tang

Patrick G Farrell

Anthony Caviglia

Paul Everhardt

Hugh Thompson

Martin J Mengele

Kevin G Faison

John Ebner

Matthew Spencer

Wade Berglund

Michael Scott

Peter Hermansen

Ka Yiu Li

A data transmitter high side switch includes at least one output unit, an input logic unit, a reset circuit coupled to the input logic unit, a capacitor pump circuit coupled to the reset circuit and the input logic circuit, and operatively to the at least one output unit. The capacitor pump circuit includes at least one capacitor that is charged in a first direction during a time period when the input data signal is in a first logic level. During a subsequent time period, when the input data signal is in a second logic level, a reference voltage for the charge on the capacitor is changed to thereby provide an overdrive level turn-on voltage to a corresponding output transistor of the at least one output unit. The charge of the at least one capacitor can be adjustably selected to compensate for tolerance variations and/or ambient conditions to control output impedance.

Data communication link with capacitor-based pumped output

Methods and apparatuses for clock signal phase measurement and control are described. In one example, a clock signal phase measurement system includes a reference clock signal line to provide a reference clock signal, a delay line to provide an output clock signal, and a wild clock. The clock signal phase measurement system includes a phase sensor configured to randomly and simultaneously sample the reference clock signal and the output clock signal utilizing the wild clock to obtain a phase data. The phase sensor is further configured to measure from the phase data a phase difference between the reference clock signal and the output clock signal.

Measurement and control of clock signal phases

Methods and apparatuses for voltage comparators are described. In one example, a circuit for a voltage comparator includes a first transistor, a second transistor for receiving a first input voltage at a second transistor gate terminal, and a third transistor for receiving a second input voltage at a third transistor gate terminal. The second transistor and the third transistor are connected to the first transistor at a first node. A fourth transistor is connected to the second transistor at a second node, and a fifth transistor is connected to the third transistor at a third node. One or more capacitors are connected between the third node and a fourth node, where the fourth node includes the second transistor gate terminal. One or more capacitors are connected between the second node and a fifth node, where the fifth node includes the third transistor gate terminal. In one example operation, the one or more capacitors provide regenerative gain.

Circuit for a voltage comparator

A digitally tuned and linearized low voltage crystal oscillator integrated circuit requires only an oscillator crystal as external circuitry. The inventive circuit operates at voltages of 3.3V and below and requires no other off-chip components. A crystal oscillator, such as a Pierce crystal oscillator uses an inverting gain stage and a phase shift network composed of an array of switchable capacitors and the crystal. The design offers improvements in power consumption, area, manufacturability and cost.

Digitally tuned and linearized low voltage crystal oscillator circuit

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

Clock recovery circuit

Growing community of inventors

Ellicott City, MD, United States of America

Eric Naviasky