Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Other

Applied Materials, Inc.

Eric N Paton

Qi Xiang

Paul Raymond Besser

Bin Yu

Robert B Ogle

Cyrus E Tabery

Paul L King

Matthew S Buynoski

Minh Van Ngo

Haihong Wang

John C Foster

William George En

Ming-Ren Lin

Minh-Van Ngo

Christy Mei-Chu Woo

Simon S Chan

Witold P Maszara

Jung-Suk Goo

Mario M Pelella

Jeff P Erhardt

Fred N Hause

Scott D Luning

Thorsten E Kammler

George Jonathan Kluth

Jacques J Bertrand

Ercan Adem

Qi Xang

Mark T Ramsbey

Peter G Borden

Arvind Halliyal

Mark S Chang

James N Pan

John A Iacoponi

Joong Jeon

Simon Siu-Sing Chan

David E Brown

Weidong Qian

Ming Lin

Austin Frenkel

Balaraman Mani

G Jonathan Kluth

Susan Tover

Matthew S Byunoski

A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

Zero interface polysilicon to polysilicon gate for flash memory

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Method of forming isolation regions for integrated circuits

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

Shallow trench isolation process

A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Method of forming a semiconductor device

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.

Method and apparatus for controlling the thickness of a selective epitaxial growth layer

A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter.

Scanning laser thermal annealing

An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

Fully depleted strained semiconductor on insulator transistor and method of making the same

An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

Shallow junction semiconductor

A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.

Interface layer between dual polycrystalline silicon layers

A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.

Methods for post offset spacer clean for improved selective epitaxy silicon growth

The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal

A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.

End-of-range defect minimization in semiconductor device

A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

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Morgan Hill, CA, United States of America

Eric N Paton