Cypress Semiconductor Corporation

Other

Eric N Mann

Harold Kutz

Erhan Hancioglu

Eashwar Thiagarajan

Amsby D Richardson, Jr

Rajiv Singh

Timothy John Williams

Galen E Stansell

John Q Torode

Monte F Mar

Toru Miyamae

Ravindra Manohar Kapre

David Michael Rogers

Sungkwon Lee

John Kizziar

Dung Ho

John J Wunner

Eric Lee Swindlehurst

Yan Yi

Vaibhav Ramamoorthy

Ryuta Nagai

Mimi Xuefeng Zhao Qian

Boo Chin-Hua

Hans Klein

Pulkit Shah

Bertrand Jeffery Williams

Yansun Xu

Ke-Cai Zeng

Marc D Hartranft

Thurman John Rodgers

Badrinarayanan Kothandaraman

James Paul Myers

Dan Zupcau

Timothy V Wright

J Kenneth Fox

Jonathan Young

Shankar Subramani

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

ESD protection circuit

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Programmable chopping architecture to reduce offset in an analog front end

One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Analog to digital converter with floating digital channel configuration

A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Method for fast detection and automatic gain adjustment in ADC based signal

A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.

A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in buffered drive mode, is further configured to operate in a blanking mode to cause the SH circuit to perform a blanking operation on the CTDAC output signal.

Digital-to-analog converter with a sample and hold circuit and a continuous-time programmable block

A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.

Dual protocol input device

A programmable logic, a memory and a microcontroller. The memory is coupled to the programmable logic circuit via the microcontroller. The programmable logic circuit, the memory and the microcontroller are fabricated as a single integrated circuit.

Microcontroller with programmable logic

A memory device () can include a memory cell block (), a standby current source (), an active current source (), and a clamping device (). In a standby mode, a standby current source () can provide constant standby current Ito memory cell block () via block supply node (). In an active mode, active current source () can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit () can provide additional current in the event a block supply node () potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well () to source () back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (), reducing overall leakage.

Current source architecture for memory device standby current reduction

A circuit () can include a first section () that can provide a designated function within an integrated circuit device that can be altered due to current injection at a node (). A mirror section () can mirror the effects of current injection on one or more devices within first section () and generate an output indication INJ_EFF representing such effects. In one very particular arrangement, detection of an injected current can be used to prevent false triggering of a switched electrostatic discharge (ESD) current path.

ESD trigger circuit with injected current compensation

An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.

Fail-safe zero delay buffer with automatic internal reference

A programmable logic device, a memory device and a microcontroller manufactured on a single integrated circuit chip. In one example, the programmable logic device may comprise one or more macrocells each comprising an input/output macrocell or a buried macrocell. In another example, the programmable logic device may be a complex programmable logic device (CPLD) or a programmable logic array (PLA).

Microcontroller with programmable logic on a single chip

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.

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Issaquah, WA, United States of America

Eric N Mann