Micron Technology Incorporated

Silicon Image Gmbh

Cisco Technology, Inc.

Advanced Micro Devices Corporation

Konica Minolta Laboratory U.s.a., Inc.

Eric N Lee

Kishore Kumar Muchherla

Akira Goda

Ali Feiz Zarrin Ghalam

Jeffrey S McNeil, Jr

Huai-Yuan Tseng

Tomoharu Tanaka

James Fitzpatrick

Qiang Tang

Dheeraj Srinivasan

Dung Viet Nguyen

Seung Ho Hwang

Yoav Weinberg

Violante Moschiano

Sundararajan Sankaranarayanan

Jeremy Binfet

Robert W Strong

William Richard Akin

Lawrence Celso Miranda

Gijung Ahn

Albert M Scalise

Paul Daniel Wolf

Hoon Choi

Dave Scott Ebsen

Jonathan Scott Parry

Gyudong Kim

Tomoko Ogura Iwasaki

Luigi Pilolli

Baegin Sung

Kaveh Shakeri

Daesik Song

Sivagnanam Parthasarathy

Patrick Robert Khayat

Xiaojiang Guo

Jung-Sheng Hoei

Dean K Nobunaga

Xiangyu Tang

David Scott Ebsen

Ugo Russo

David C Lee

Leonid Minz

Jano D Banks

Matthew Kuhlke

Fadi Ramzi Jabbour

Sheyang Ning

Ook Kim

Lakshmi Kalpana Vakati

Stephen J Keating

John D Banks

Duane P Siemens

Tong Liu

Keewook Jung

Zeehoon Jang

Nam Hoon Kim

Cobie B Loper

Vamsi Pavan Rayaprolu

Ching-Huang Lu

Johnny Hsienchow Lee

Ramin Ghodsi

June Lee

Umberto Siciliani

Daniel J Hubbard

James D Lyle

Adrian Sfarti

Giovanni Maria Paolucci

Sead Zildzic, Jr

Sead Zildzic

Paing Z Htet

Glenn Inn

Floriano Montemurro

William Sheet

Junwyn A Lacsao

Michael Schumacher

Eddie Wang

Lakshmi Kalpana K Vakati

Vladimir Grekhov

Haibo Li

Robert Loren O Ursua

Balakrishnan Thoppaswamy

Chang-Hwa Lee

Eddie Howard

Feng Ding

Simon Lian

Vinod Jani

Yevgen Goryachok

A memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. The processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.

Status polling based on die-generated pulsed signal

A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Corrective reads with improved recovery from data retention loss

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Double single level cell program in a memory device

Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

Validating read level voltage in memory devices

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving, from a memory sub-system controller, a first read command and a second read command; determining that the memory device is in a suspended state; and responsive to determining that a first address range specified by the first read command does not overlap with a second address range specified by the second read command, issuing, to the memory device, the first read command and the second read command collectively.

Memory performance during program suspend protocol

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

Memory devices with backside bond pads under a memory array

A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

Workload-based scan optimization

Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Adaptive pre-read management in multi-pass programming

Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Sacrificial strings in a memory device to detect read disturb

Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.

Single-level cell program-verify, latch-limited data recovery

A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Write-once memory encoded data

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Memory device programming technique for increased bits per cell

A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

Resumption of program or erase operations in memory

A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Conditional valley tracking during corrective reads

Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same

Growing community of inventors

San Jose, CA, United States of America

Eric N Lee