International Business Machines Corporation

Digeo, Inc.

Eric N Lais

David F Craddock

Thomas Anthony Gregg

Matthias Klein

Steve Thurber

Matthew J Kalos

Dan F Greiner

Gregory Michael Nordstrom

Donald R DeSota

Harry M Yudenfriend

Steven Mark Thurber

Beth A Glendening

Jeffrey C Hanscom

Srinivas Kotta

John M Pritz

Mark S Farrell

Peter Grimm Sutton

Bruce H Ratcliff

Gustav E Sittmann, Iii

Jesse Paul Arroyo

Richard Loise Arndt

Adalberto Guillermo Yanes

Janet R Easton

Michael James Becht

Sascha Junghans

Benjamin Herrenschmidt

Bruce Michael Gilbert

Edward W Chencinski

Scott A Brewer

Sakethan R Kotta

Rama K Hazari

Mark Greenberg

Manish Shah

Rob Joersz

Donald W Schmidt

Jeffrey A Stuecheli

Charles Ray Johns

Maged M Michael

Peter Kenneth Szwed

Douglas J Griffith

Robert J Safranek

Guerney D H Hunt

Frank William Brice

Debapriya Chatterjee

Michael Grassi

Robert Joersz

Gerd Konrad Bayer

Michael Jung

Elke G Nass

Kumaraswamy Sripathy

Darwin W Norton, Jr

Ashley Lim

Steven G Wilkins

A computer system, computer readable storage medium, and computer-implemented method for detecting if one or more processing devices have separately sourced power feeds. The method includes determining transmission of a first signal in a first electric path. The method also includes monitoring for a second signal in a second electric path that is different from the first electric path. The method further includes determining, subject to the monitoring, electrical isolation between the first electric path and the second electric path. The claimed computer-implemented method dynamically, and automatically, determines that power sources are separate, isolated, and redundant.

Detecting redundant power feeds

A single input/output (I/O) controller for both secure partitionable endpoints (PEs) and non-secure PEs is enabled in a trusted execution environment (TEE) where secure memory portions are isolated from non-secure PEs. Security attributes for certain endpoints indicate secure memory access privilege of owning entities of the certain endpoints. A security monitor has exclusive access to the address translation control tables (TCE) stored in secure memory associated with a secure endpoint. When owning entity reassignment occurs, the endpoints are reinitialized to support a change in ownership from an outgoing owning entity having secure memory access and an incoming owning entity not having secure memory access.

Secure memory isolation for secure endpoints

Managing direct memory access (DMA) by: defining a translate control entity (TCE) cache flag for cache memory addresses, receiving a DMA TCE related request, checking the TCE cache flag status, and completing the TCE related request according to the TCE cache flag status.

Managing direct memory access

A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations

Peripheral component interconnect express (PCIE) network with input/output (I/O) chaining to reduce communication time within execution of I/O channel operations

A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.

Synchronous input/output computer system including hardware invalidation of synchronous input/output context

A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

Transmission of a message based on a determined cognitive context

In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Configurable I/O address translation data structure

Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.

Peripheral component interconnect express (PCIE) pseudo-virtual channels using vendor defined messages

A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Synchronous input / output hardware acknowledgement of write completions

A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Flexible I/O DMA address allocation in virtualized systems

A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Input/output computer system including hardware assisted autopurge of cache entries associated with PCI address translations

Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

Management of data transaction from I/O devices

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Tillson, NY, United States of America

Eric N Lais