Other

Micron Technology Incorporated

Trellis Phase Communications, LP

Rpx - Nw Acquisition, LLC

University of Texas System

Rpx Corporation

Nextwave Solutions, LP

E.o. Communication Fund, LLC

East Texas Technology Partners, LP

Round Rock Research, LLC

Rpx - Nw Aquisition, LLC

Rpx-nw Aquistion LLC

Geobrowser Innovations, LP

Eric Morgan Dowling

John P Fonseka

Mark Nicholas Anastasi

Robert Abe Westerlund

Duncan Leo MacFarlane

Zifei Wang

Richard M Golden

Duncan Leo Mac Farlane

Umesh Jani

Mark Nicholus Anastasi

The present invention provides a design framework that is used to develop new types of constrained turbo block convolutional (CTBC) codes that have higher performance than was previously attainable. The design framework is applied to design both random and deterministic constrained interleavers. Vectorizable deterministic constrained interleavers are developed and used to design parallel architectures for real time SISO decoding of CTBC codes. A new signal mapping technique called constrained interleaved coded modulation (CICM) is also developed. CICM is then used to develop rate matching, spatial modulation, and MIMO modulation subsystems to be used with CTBC codes and other types of codes. By way of example, embodiments are primarily provided for improved 5G LTE and optical transport network (OTN) communication systems.

Constrained interleaving for 5G wireless and optical transport networks

Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems.

Encoding and decoding using constrained interleaving

A smart card is used with a network based system to providing portable telecommunication and computing services. In an exemplary embodiment the smart card holds a user authentication code and user telephony account information. The smart card transfers the user authentication code and the account information to one of a plurality of geographically dispersed card readers which are each connected to a local telephony device. When the smart card is plugged into a first card reader, telephone calls directed to the smart card user's follow-me telephone number are received at a first local telephony device. When the smart card is plugged into a second smart card reader, telephone calls directed to the follow-me telephone number are received at a second telephony local device. Hence the user is enabled to receive and place calls using any of the geographically dispersed telephony devices as though they were his/her own personal landline or cellular telephone supplied by his/her telephony services provider.

Methods and systems for providing portable VoIP services

Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. Constrained interleaving can be summarized in that it: 1) uses an outer code that is a block code or a non-recursive convolutional code, and as such, there are multiple codewords present in the constrained interleaver, 2) selects a desired MHD, 3) selects an interleaver size and a set of predefined interleaver constraints to prevent undesired (low-distance) error events so as to achieve the desired MHD, and 4) performs uniform interleaving among the allowable (non-constrained) positions, to thereby maximize or otherwise improve the interleaver gain subject to the constraints imposed to maintain the desired MHD.

Methods, apparatus, and systems for coding with constrained interleaving

A network scanner, communication protocols, and client and server programs and are provided which provide an improved way to transmit legally binding documents, obviating the need for outmoded, legacy fax transmissions. Using the network scanner, a document may be scanned and transferred directly into any shared folder inbox residing on any computer attached to the Internet. Enhanced server systems and network communications and messaging protocols are provided that are more practical to use than email for sending documents such as executed legal documents or other documents requiring robust integrity and authenticatability. Similarly, the inventive network scanner, server systems and communication protocols provide improved ways to perform large file transfers and to manage bandwidth to minimize problems associated with uploading/downloading large files as attachments to/from email servers and for enabling user control over VoIP quality during file transmission sessions.

Network scanner for global document creation, transmission and management

Methods, smart cards, and systems for providing portable computer, VoIP, and application services

Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented.

Hard iterative decoder for multilevel codes

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

Split embedded DRAM processor

Growing community of inventors

Holmes Beach, FL, United States of America

Eric Morgan Dowling