Soitec

Saint-augustin Canada Electric Inc.

Stmicroelectronics S.a.

Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Eric Mazaleyrat

Rainer Klaus Krause

Frank Dimroth

Eric Guiot

Richard P Fournel

Cécile Aulnette

Cecile Aulnette

Charlotte Drazek

The present invention relates to an assembling method for a base plate of a concentrated photovoltaic module comprising the steps of: assembling a heat sink on the base plate; and assembling a photovoltaic cell assembly on the heat sink after the heat sink has been assembled on the base plate.

High accuracy module assembly process

This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.

Advanced CPV solar cell assembly process

This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.

Multiple transfer assembly process

An integrated circuit including logic MOS transistors, EPROM cells, and high-voltage MOS transistors. Each EPROM cell includes a floating gate formed from a first polysilicon level above a tunnel oxide and a control gate formed from a second polysilicon level. Each logic MOS transistor includes a gate formed from a portion of the second polysilicon level above a very thin oxide. Each high-voltage transistor includes a gate corresponding to a portion of the first polysilicon level above a layer of said tunnel oxide, the gate being covered with a portion of the second polysilicon layer, except at locations where a contact is desired to be made with the gate. The uncovered portion of the first polysilicon layer in the high-voltage MOS transistors is coated with a silicon nitride layer.

Integrated circuit including high-voltage and logic transistors and EPROM cells

Growing community of inventors

Crolles, France

Eric Mazaleyrat