Adtran Gmbh

Eric Malcolm Rives

Andrew T Ruble

Matthew A Kliesner

David H Nabors

Matthew Gann

Timothy G Mester

Joseph Lee Boyd

Jonathan Brock McDonald

Anthony A Goodloe

Methods and apparatus for communicating synchronous digital signals through an asynchronous domain are disclosed. In one aspect a method includes receiving a first synchronous digital signal of a first domain, wherein the first synchronous digital signal is generated by a first device for communication to a second device; encapsulating the first synchronous digital signal of the first domain into a first asynchronous packet of a second domain; and transmitting the first asynchronous packet to an asynchronous network of the second domain.

Synchronous digital signal encapsulation

In order to configure and monitor the operation of a span-powered T1 radio, use is made of the out-of-band facility data link channel that is available within an extended superframe of the T1 digital data stream transported between an indoor carrier services unit and the T1 framer of the radio. The facility data link channel is employed to transport packetized configuration and status information between the indoor carrier service unit and the span-powered T1 radio.

Use of T1 facility data link to transport status and configuration data packets for loop-powered T1 radio

A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase delayed versions of the input clock signal and feeds a multiplexer that is controllably operative to couple one of the outputs of the fixed fractional delay line to a regenerated clock output port. A control loop, which includes the FIFO storage buffer, the output port and a steering control input of the multiplexer circuit, is operative to selectively change which output of the fixed fractional delay line is coupled by the multiplexer to the output port, so as to controllably cause the output clock signal to track the effective frequency of the valid data signal.

Data buffer-controlled digital clock regenerator

A loop-powered T1 digital radio is coupled to a powered T1 wireline. The radio not only interfaces digital T1 communication signals with the line, but is configured to extract and convert electrical power from the line to voltages necessary for operating the radio. The loop-powered T1 radio transmits and receives RF energy containing the T1 digital communication signals with respect to a remote digital radio, such as a 'blue tooth' type radio.

Loop-powered T1 radio

A high bit rate digital subscriber line (HDSL) communications scheme employs a serialized multiplexer&mdash;demultiplexer protocol, that enables both HDSL channels to be successfully transmitted over an asynchronous, serialized communication link. A service channel supplies control information used by a far end device to extract each HDSL channel from the serialized bit stream. A data channel interface circuit combines a pair of data channel segments of two 784 kbps HDSL channels into a standard 1.544 Mbps T1 serial data stream. The data channel interface circuit contains a register bank which stores embedded operations channel (EOC) information extracted from the two HDSL channels. Auxiliary HDSL signaling information stored in the data channel interface circuit is controllably accessed by a communications control processor for application to an output multiplexer. A framer unit supervises the operation of output multiplexer controllably and injects auxiliary (framing and time alignment) service channel signals to the output multiplexer. The framing structure of the serialized HDSL protocol provides a contiguous sequence of framing bits, HDSL asynchronous channel bits, bit-stuffing majority bits, a stuffing bit, a signaling bit, and 1.544 Mbps T1 payload bits.

Serialized HDSL multiplexer - demultiplexer protocol

A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.

Growing community of inventors

Hampton Cove, AL, United States of America

Eric Malcolm Rives