Xilinx, Inc.

Tendril Networks, Inc.

Uplight, Inc.

Eric M Shiflet

W Story Leavesley, Iii

Emil S Ochotta

William W Stiehl

Jason J Moore

Ian L McEwen

Reto Stamm

Nij Dorairaj

John D Corbett

A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.

Setpoint adjustment-based duty cycling

A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.

Isolation verification within integrated circuits

Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.

Method and apparatus for partial reconfiguration circuit design for a programmable device

A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.

Method and apparatus for circuit design closure using partitions

A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.

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Boulder, CO, United States of America

Eric M Shiflet