Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Eric M Apelgren

Paul Raymond Besser

Christian Zistl

Jonathan B Smith

Jeremy Isaac Martin

Srikanteswara Dakshina-Murthy

Nicholas John Kepler

Lie Larry Zhao

Fred Cheung

Nick Kepler

Larry Zhao

Gerald W Barnett

Darrell A Harris

Nabil R Yazdani

Srikantewara Dakshina-Murthy

A method of forming an electronic device is provided that includes forming a resist layer over a substrate having a first region, a second region, and a third region. The method further includes directing radiation through a reticle, wherein the reticle comprises different radiation zones having significantly different transmission values with respect to each other, and the first region is exposed to a significantly different amount of radiation as compared to the second region. The method also includes removing part of the resist layer to leave a remaining portion such that the second region of the resist layer is significantly thinner than the third region of the resist layer, and then ion implanting the substrate while the remaining portion of the resist layer overlies the substrate to form a first implant region and a second implant region having different depths.

Methods of forming electronic devices by ion implanting

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Resist trim process to define small openings in dielectric layers

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Locally increasing sidewall density by ion implantation

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.

Method of defining small openings in dielectric layers

The present invention is directed to semiconductor processing operations. In one illustrative embodiment, the invention comprises providing a wafer having a layer of photoresist formed thereabove, positioning the layer of photoresist in contact with a polishing pad or a polishing tool, and rotating at least one of the wafer and the polishing pad to remove substantially all of the layers of photoresist.

Photoresist removal using a polishing tool

A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

Semiconductor device with partial passivation layer

A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

A Visual Basic software program to automate the procedures required for energy dose verification and adjustment of the ASM photoaligner. The software program has the capability of manipulating the ASM photoaligner through a resident software routine of the photoaligner. In addition, the software program has a user interface which prompts the operator for inputs and instructs the operator on what is required to perform the energy dose calibration. This ensures a reproducible procedure regardless of the photoaligner being tested or the operator doing the testing. Automating this procedure allows changing the photoaligner energy dose through the ASM Machine Constants (values stored in the ASM photoaligner that control the operation of the photoaligner). If the input data is out of specification the program will either reference a trouble shooting guide or request that the specific procedure be repeated for verification. After collecting the data from the operator, the program makes the necessary calculations and compares the results to a predefined data base which contains the specification limits for each of the individual photoaligners. Besides saving time, automating these procedures ensures that all operators perform them the same way, thereby eliminating operator-to-operator variation. Furthermore, it will no longer be necessary to open the ASM electronics cabinet to adjust the shutter control board potentiometer for brining the dose back to specification and by making the changes through software it will be possible to track them over time.

Method for automated energy dose measurement and adjustment for a

Apparatus and method for inhibiting the image of a transparent, undesired feature on a reticle from printing on semiconductor material. The apparatus includes a frame attachment connected to a pellicle frame that is attached to a reticle. A blade that is opaque to ultraviolet light is moveable across the frame attachment and may be positioned proximate the undesired feature of the reticle to prevent the printing of the image of the undesired feature on the semiconductor material. The blade may be positioned above the undesired feature to inhibit ultraviolet light from an illumination source from impinging upon the undesired feature. Alternatively, the blade may be positioned below the undesired feature to inhibit ultraviolet light passing through the undesired feature from impinging upon the semiconductor material.

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Austin, TX, United States of America

Eric M Apelgren