Texas Instruments Corporation

Eric Louis Pierre Badi

Laurent Le Faucheur

Frederic Danis

Philippe Francois Georges Gentric

Yves Michel Marie Massé

Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

12C bus controller slave address register and command FIFO buffer

I2C controller register, control, command and R/W buffer queue logic

In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Clock drift compensation interpolator adjusting buffer read and write clocks

A network of processing devices includes a medium for low-latency interfaces for providing point-to-point connections between each of the processing devices. A switch within each processing device is arranged to facilitate communications in any combination between the processing resources and the local point-to-point interfaces within each processing device. A networking layer is provided above the low-latency interface stack, which facilitates re-use of software and exploits existing protocols for providing the point-to-point connections. Higher speeds are achieved for switching between the relatively low numbers of processor resources within each processing device, while low-latency point-to-point communications are achieved using the low-latency interfaces for accessing processor resources that are external to a processing device.

Low-latency interface-based networking

Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer and a size to define a corresponding one of the plurality of buffers. Transferring data in any one of the plurality of buffers by using a control function within an accessing module to generate a buffer address by accessing and updating the address pointer in the corresponding descriptor. In a processor that accesses the circular buffers, the control function is one or more complex instructions tailored for computing read and write addresses to access the circular buffer using fields within the corresponding descriptor. In a DMA module that accesses the circular buffers, the control function is a hardware controller that computes read and write addresses using the fields within the corresponding descriptor to access the circular buffer.

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Cagnes sur Mer, France

Eric Louis Pierre Badi