Rambus Inc.

Eric Linstadt

Trung Am Diep

Brent Steven Haukness

Yohan Usthavia Frans

Jun Y Kim

Simon Li

J James Tringali

Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.

Wear leveling in a memory system

A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Synchronous wired-OR ACK status for memory with variable write latency

A method of reading data from a memory device is disclosed. The method comprises accessing preexisting data from a location in the memory device in response to a read command and identifying an error in the preexisting data. The identified error is corrected for transmission as corrected data. Error information representing the identified error is stored while the preexisting data is retained in the location of the memory device in uncorrected form.

Memory device with ECC history table

Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.

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Palo Alto, CA, United States of America

Eric Linstadt