Cypress Semiconductor Corporation

Other

Eric Lee Swindlehurst

Timothy John Williams

Eric N Mann

Toru Miyamae

Ravindra Manohar Kapre

David Michael Rogers

Sungkwon Lee

Dung Ho

Yan Yi

Ryuta Nagai

Mimi Xuefeng Zhao Qian

Boo Chin-Hua

Yen-Cheng Kuan

Shiuh-hua Wood Chiang

Yixin Song

Jensen Hunter

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

ESD protection circuit

The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies.

Time-interleaved successive approximation register analog to digital converter with grouped digital to analog capacitors

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Marysville, WA, United States of America

Eric Lee Swindlehurst