Lattice Semiconductor Corporation

Koninklijke Philips Corporation N.v.

Eric Lee

Wei Han

Zheng Chen

Warren Juenemann

Barry Britton

Mose Wahlstrom

Kanad Chakraborty

Jie Qin

Shankar Durgamahanthi

Dan Ratchen

In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Highly secure and extensive scan testing of integrated circuits

In one embodiment, a programmable logic device such as an FPGA includes a programmable fabric adapted to operate normally and in a sleep mode, and a general purpose input/output port (I/O). The I/O port is adapted to function in conventional fashion during normal operation of the programmable fabric and as a wakeup control port during the sleep mode.

Programmable logic device wakeup using a general purpose input/output port

A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.

Safe programming of key information into non-volatile memory for a programmable logic device

Growing community of inventors

Allentown, PA, United States of America

Eric Lee