International Business Machines Corporation

International Business Corporation

Eric Lallemand

Fabrice Jean Verplanken

Alain R Blanc

Rene J Glaise

Gilles Toubol

Jean-Claude Abbiate

Patrick J Jeanniot

Hans Rudolf Schindler

Francois Kermarec

Tan T Pham

R Glaise

The swapping function of input values to output values is performed through a pseudo content addressable memory which provides output values corresponding to a number E of n-bit input values, with E&equals;2 &minus;1. The pseudo content addressable memory is made of a plurality of cascaded random address memories having at least a 2 addressing capability, with d higher than p. A control logic circuit is provided to store into each random access memory p-bits pointers, with each pointer being different from the others and randomly assigned to an input value. In order to find an output value corresponding to an input value, the control logic circuit sequentially address and reads the cascaded random access memories, the first memory being addressed with a part including a number n1 of bits of the input value, and each one of the next memories being addressed with the pointer read from the preceding memory concatenated with another part ni of bits of the input value, with ni equal to or lower than n&minus;n1. The output value is found as a result of the addressing of the last memory.

Apparatus for swapping input values into corresponding output values

A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of a message sent over a connection and segmented into a finite number of packets in a fixed size packets network. The process is implemented in the adapter cards of the ATM network access nodes (2, 4) located at the boundary of the ATM network. These nodes, when supporting AAL5 type ATM connections, reassemble messages which have been segmented at the entry of the network and to calculate the FCS of the message cell payloads for data integrity checking. The process of the invention starts at each reception of a cell with the calculation of a partial FCS (10) performed in parallel to the connection control block fetching phase (40); these 2 parallel operations allow FCS checking during the cell processing time of connections established over medium and high speed lines.

Method and apparatus for fast checking the frame check sequence of a

A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.

Predictive clock recovery circuit

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La Gaude, France

Eric Lallemand