Alliant Computer Systems Corporation

Raster Technologies, Inc.

Eric L Ryherd

Ross G Werner

John G Torborg, Jr

Disclosed is a three-dimensional display system that utilizes a host processor for performing geometric transformations and a local display processor for processing the user-supplied information which defines the object to be displayed. The display processor creates image data defining the location, color and intensity of each point of the overall image. This display processor processes and stores depth data which defines the corresponding depth relationships of the image points at each location of the overall image with the depth data being stored in a depth buffer, which is part of the display processor. The depth buffer is a two port memory device with one port being a random access port and the other being a serial access port. The display processor pieplines depth buffering operations by loading a row of data from the depth buffer into a shift register and then reading (a Read operation) the relevant pixel data through the serial access port which is connected to the shift register. The display processor then performs the Compare operation between the depth of the new pixel data and the depth of the old pixel data and if appropriate, will perform a Conditional Write operation o=f the new pixel data. The Write operation is performed through the random access port. As a result, the serial access port can continually be used for Read operations during each and every clock cycle, and the random access port can be used for Conditional Write operations during each consecutive clock cycle as well.

Apparatus and method for performing depth buffering in a three

The invention is a method and apparatus primarily for generating pixel representations for the video display of three-dimensional objects projected onto a two-dimensional pixel plane. The scanlines of the pixel plane are associated into N interlaced sets, each set having as members only scanlines having an equivalent vertical pixel location Modulo N. The image memory unit block utilizes both serial and parallel processing. For each color (red, green and blue) and for calculating depths, each image memory unit has a plurality N of Scanline Processors for generating the color or depth data to assign to a given pixel. Each of the Scanline Processors is associated with exactly one of the N sets of scanlines. The image memory units each also include a Master Controller. For certain objects, particularly triangular patches, the Master Controller sets up sequentially each Scanline Processor to render pixels on a specific scanline. As the Scanline Processor is rendered pixels, the Master Controller sets up the next scanline processor, and so on, until the entire patch is rendered. For other constructs, such as non-horizontal vectors, the Master Controller sets up all of the N Scanline Processors simultaneously with all of the data necessary to render the entire vector. Each Scanline Processor determines the location of pixels representing the vector and also calculates data with resepct to each pixel. Each scanline processor only writes to memory that data with respect to pixels of scanlines assigned to the set with which each Scanline Processor is associated.

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Brookline, MA, United States of America

Eric L Ryherd