Hewlett Packard Enterprise Development LP

Eric L Pope

Melvin K Benedict

Reza Mushtag Bacchus

Andrew Christopher Walton

Chi Kim Sides

Stephen F Contreras

Chun-Pin Huang

Nigel John Edwards

Lidia Warnes

Erin Antony Handgen

Scott P Faasse

Richard Cheung

In some examples, a memory device includes a plurality of rows of memory cells, a plurality of victim counters associated with respective rows of memory cells of the plurality of rows of memory cells, and a plurality of aggressor counters associated with the respective rows of memory cells. A first victim counter of the plurality of counters is associated with a first row of the plurality of rows of memory cells, the first victim counter to advance in response to advances in counts of aggressor counters associated with neighboring rows of memory cells that are neighbors of the first row.

Victim row counters in memory devices

Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.

Memory module authentication extension

Systems and methods are provided for binding one or more components to an identification component of a hardware module. Each of the serial numbers for the one or more components are included within a module-specific authentication certificate that is stored within the identification component of the hardware module. When connected to a computing platform, an authentication system of the computing platform is capable of retrieving the module-specific authentication certificate. The authentication system can compare the list of serial numbers included in the module-specific authentication certificate with one or more serial numbers read over a first interface. If the two lists of serial numbers match, the authentication system can flag the hardware module as authenticate through authentication of all components of the hardware module.

Field-replaceable unit (FRU) secure component binding

Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.

Row hammer detection and avoidance

One embodiment provides a memory module that enables online repair of defective memory cells. The memory module includes a memory array storing data, a self-test controller coupled to the memory array and configured to perform a self-test on a region within the memory array without interrupting operations of the memory module, and a memory-repair module configured to repair a defective memory cell identified by the self-test controller.

System and method for detecting and repairing defective memory cells

A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.

Memory access rate

One embodiment provides a memory module. The memory module includes a plurality of rows of memory cells, with a respective row comprising one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells, and a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to the disturbance to the canary memory cell exceeding a predetermined threshold.

System and method for detecting memory cell disturbance by monitoring canary cells

In some examples, a system obtains error correction data for data stored in a memory, produces entropy data using the error correction data, adds the produced entropy data to a pool of entropy data, and performs a security operation using selected entropy data from the pool of entropy data.

Entropy data based on error correction data

An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Quality of service based memory throttling

In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

Physical memory region backup of a volatile memory to a non-volatile memory

Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

Validation of a repair to a selected row of data

In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.

Post package repair for mapping to a memory failure pattern

A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Volatile memory device with automatic lower power state

Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Growing community of inventors

Tomball, TX, United States of America

Eric L Pope