Texas Instruments Corporation

Eric L P Badi

Serge Bernard Lasserre

Robert J P Nychka

Jonathan Y Zhang

Apparatus and method for employing a Hardware Processing Function in a processor system using a hierarchical memory. Embodiments of the disclosed invention may be used to enhance processor performance and functionality while maintaining cache coherency and reducing cache pollution. A system includes a processor, a hierarchical memory system coupled to the processor, and a Hardware Processing Function coupled to the hierarchical memory system. The processor is configured to decode an instruction and the hierarchical memory system is configured to execute the instruction. The instruction directs the memory system to perform a data manipulation. The processor transfers a value to the memory system. The value comprises a location of source data to be manipulated, a selection of a Hardware Processing Function to perform the data manipulation, and a destination storage location where the manipulated data is to be stored.

Processing function connected to processor memory hierarchy

Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.

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Cagnes-sur-Mer, France

Eric L P Badi