Texas Instruments Corporation

Eric L Badi

Jean-Marc Philippe Bachot

Bryan David Sheffield

Stephen Wayne Spriggs

Vikas K Agrawal

Gerard Chauvel

Serge Bernard Lasserre

Gilbert Cabillic

Jean-Philippe Lesot

Dominique D'Inverno

Gilbert Laurenti

Douglas E Deao

Mark L Buser

Shigeshi Abiko

Jean-Pierre Giacalone

Marc Couvrat

Herve Catan

Laurent Le-Faucheur

Armelle Laine

Karim Djafarian

Vincent Gillet

Anne Lombardot

Gael Clave

Francois Theodorou

Yves Masse

Alain Boyadjian

Jean-Louis Tardieux

Laurent Ichard

Emmanuel Ego

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Frederic Nidegger

David Russell

N M Ganesh

In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Clock drift compensation applying paired clock compensation values to buffer

A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.

Micro-sequence based security model

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Self-clocking memory device

Method of operating a memory at high speed using a cycle ready status output signal

An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper () incorporating self-timing logic () and a mux () is used to couple a single access memory core () to a memory interface unit (). The memory interface unit () couples a central processing unit () to the memory wrapper (). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle. In accordance with another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) (). In another embodiment of the invention, a memory core (embodied within RAM) incorporating the self-timing architecture is incorporated directly into the processor core thereby avoiding the need for a memory wrapper and the time delay associated with passing information from the processor core via the memory interface unit and to the memory core. Direct incorporation of a memory core into the processor core facilitates more intensive accessing and additional power savings. In accordance with yet another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) () is further incorporated into an electronic computing system, such as a digital cellular telephone handset ().

Method and apparatus for accessing a memory core multiple times in a single clock cycle

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper ( ) incorporating self-timing logic ( ) and a mux ( ) is used to couple a single access memory core ( ) to a memory interface unit ( ). The memory interface unit ( ) couples a central processing unit ( ) to the memory wrapper ( ). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle. In accordance with another aspect of the invention, the apparatus and method for using self-timing logic to make at, least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) ( ). In another embodiment of the invention, a memory core ( embodied within RAM 206) incorporating the self-timing architecture is incorporated directly into the processor core thereby avoiding the need for a memory wrapper and the time delay associated with passing information from the processor core via the memory interface unit and to the memory core. Direct incorporation of a memory core into the processor core facilitates more intensive accessing and additional power savings.In accordance with yet another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP)( ) is further incorporated into an electronic computing system, such as a digital cellular telephone handset ( ).

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Cagnes sur Mer, France

Eric L Badi