Intel Corporation

Eric Kwesi Donkoh

Muhammad M Khellah

Tanay Karnik

Gautham N Chinya

Jaydeep P Kulkarni

Iqbal Rajwani

Julien Sebot

Sapumal Wijeratne

Bibiche M Geuskens

Stephen J Tarsa

Rangeen Basu Roy Chowdhury

Rustam Miftakhutdinov

Ataur Patwary

A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning

Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower V, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.

Reduced swing bit-line apparatus and method

Described is an apparatus which comprises: a memory cell with a data port; and a logic gate, coupled to the data port of the memory cell, to generate a data word-line signal according to data on the data port and an asynchronous word-line signal, wherein the logic gate is operable to gate data on the data port during low power mode.

Low power register file

A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of its bit cells and domino logic for each of its bit line. Each bit line of the memory device is coupled with a gating logic that is activated using a clocked signal. This eases the timing requirement of the read word lines of the memory device and the read word lines do not form the critical path of the access time of the memory device. The leakage current of the memory device in inactive mode is reduced by switching off the pre-charge circuit and/or the keeper circuit of each bit line. Each bit line is pre-charged on demand prior to the evaluation of each bit line.

Methods and systems to read register files with un-clocked read wordlines and clocked bitlines, and to pre-charge a biteline to a configurable voltage

Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such 'normally Low' evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.

Register file circuits with P-type evaluation

A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines.

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Hillsboro, OR, United States of America

Eric Kwesi Donkoh