Adv Antest Corporation

Eric Kushnick

Roland Wolff

Mei-Mei Su

Michael Frank Jones

Ben Rogel-Favila

James Fishman

Yasuo Furukawa

James Getchell

Lawrence Kraus

Masahiro Ishida

Takahiro Yamaguchi

Harry Hou

Gerald Chan

Kenji Inaba

Alan S Krech

Andrew Niemic

Toshiyuki Miura

A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.

Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array

Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently

In an embodiment, a universal test cell includes a plurality of test slots configured to receive a plurality of universal test containers each including similar dimensions. Each universal test container is configured to enclose each of a plurality of different devices to test. Each universal test container includes an external electrical interface configured to couple to each of the plurality of different devices to test. The universal test cell is configured to test the plurality of different devices while each is located within a universal test container of the plurality of universal test containers. The universal test cell includes a plurality of universal electrical interfaces that are each configured to couple with the external electrical interface of each universal test container.

Universal test cell

In one embodiment, a universal test container can include a universal external electrical interface configured to couple to each of a plurality of different devices to test. In addition, the universal test container is configured to enclose each of the plurality of different devices to test.

Universal container for device under test

In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.

Universal test floor system

A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

High speed tester communication interface between test slice and trays

Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Histogram generation with mixed binning memory

There is provided a correcting apparatus for correcting a PDF obtained from a measurement result of measuring a characteristic of a measurement target at strobe timings including errors with respect to ideal timings at predetermined intervals, the correcting apparatus including: an interpolation section that is supplied with a CDF of the measurement result, interpolates a value between each strobe timing of the CDF, calculates a value of the CDF at each of the ideal timings, and calculates a corrected CDF at the ideal timings; and a corrected function generating section that generates a corrected PDF in which the errors of the strobe timings for the PDF have been corrected, based on the corrected CDF calculated by the interpolation section.

Correcting apparatus, PDF measurement apparatus, jitter measurement apparatus, jitter separation apparatus, electric device, correcting method, program, and recording medium

Disclosed is a method and apparatus for calibrating a time vernier in an automatic test equipment (ATE) system, the method including generating a data signal and a reference signal whose periods differ by a small amount (dt), using precession of the data signal and reference signal to create accurate delay increments, and creating a trigger signal for Bit Error Rate Test (BERT) counting, the trigger signal having a select frequency such than an integer number (N) of triggers are generated with a precession period (TC). Upon occurrence of each trigger, a BERT is initiated for measuring data to determine strobe positions with respect to the data signal.

Method and apparatus for time vernier calibration

Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Histogram generation with banks for improved memory access performance

A method and apparatus for synchronizing digital and analog/mixed signal modules in a test site of an open architecture test system is disclosed. Event triggers from digital modules are routed to an ASYNC module, which selectively distributes them to analog/mixed signal modules. When an event occurs, the trigger may activate an analog/mixed signal module to perform a certain operation. The ASYNC module may also receive triggers from the analog/mixed signal modules and selectively distribute them back to the digital modules or analog/mixed signal modules. The digital modules can be programmed to wait for an analog/mixed signal module to complete an operation, as indicated by a trigger received from that analog/mixed signal module, before continuing. Because embodiments of the present invention enable synchronization of digital and analog/mixed signal modules under pattern control, synchronization can be very precise and repeatable as compared to synchronization from a site controller.

Synchronization of modules for analog and mixed signal testing in an open architecture test system

A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M 'fabric' speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.

Fabric-based high speed serial crossbar switch for ATE

The present invention is directed to the use of a DDS to generate a high purity reference signal with high frequency resolution by switching a frequency tuning word (FTW) between particular values for particular time durations to produce two or more closely spaced frequencies that appear at the DDS output as a single frequency. Given a DDS switching between Fand Fsuch that Fis present for time Tand Fis present for time T, with the total period of the repeating pattern being T=T+T, in order for the output of the DDS to produce a single high-purity frequency that is the time-weighted average of the alternating frequencies, the condition |F&#x2212;F|&#x3c;&#x3c;&#x3c0;/T must be satisfied. The time-weighted average frequency Favg=(T&#xb7;F+T&#xb7;F)/(T+T). By an appropriate choice of Tand T, Favg can be set to any frequency between these two frequencies.

Method and apparatus for improving the frequency resolution of a direct digital synthesizer

A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Growing community of inventors

Santa Clara, CA, United States of America

Eric Kushnick